Optimization Techniques for the TI C6000 Compiler
From Texas Instruments Embedded Processors Wiki
Translate this page to
This topic outlines some of the key optimization techniques you can apply to get the most leverage out of the c6000 TI Code Generation Tools.
Contents |
Introduction to C6000 DSP Optimization
- Introduction to C6000 DSP Optimization This application report helps DSP newcomers optimize their code for the C6000 family of DSPs.
C6000 Optimization Workshop and Materials
- TMS320C6000 DSP Optimization Workshop
- The workshop materials on this page show a user how to optimize their high-level C code for the TMS320C6000 DSP.
- Scroll down to "Workshop Materials"
c64, c64Plus Compiler Overview
- C64plus_cgt_overview.pdf
- Compact instructions, sploop, trampolines, performance/codesize data for c64x+ and a very brief splattering of tuning tips
c64, c64Plus Optimization Techniques
- C64p_cgt_optimization.pdf
- Selecting the right build options
- Also adds intermediate/advanced techniques for optimizing structure accesses, using restrict with structures and new examples.
- Examples use cgt version 6.0.x.
- Good data on control code optimizations
Hand-Tuning Loops and Control Code on the TMS320C6000
- Detailed Application Report
- The TMS320C6000 compiler automatically performs a great deal of performance-related tuning. This compiler-driven optimization usually suffices. For the occasional cases where additional CPU performance is needed, this application report presents strategies and examples for improving performance of C/C++ applications. Memory-related performance improvements (such as background DMA transfers or cache usage) are outside the scope of this report. The techniques apply to all members of the C6000 architecture family.
- The target audience is intermediate to advanced application developers. Familiarity with the C6000 architecture and experience developing code for this architecture is assumed.
