Oscillator fault reasons

From Texas Instruments Embedded Processors Wiki

Contents 1 Oscillator fault reasons on MSP430 processors 1.1 Hardware based quartz failures 1.1.1 Load capacitance 1.1.2 Parasitic capacitances 1.2 Software based quartz failures 1.3 Other reasons for a quartz failure 1.3.1 Usage of a debugger

Oscillator fault reasons on MSP430 processors

Besides the internal oscillators, which are usually RC based and therefore have high tolerances and low temperature stability, all MSPs offer ways to attach one or more external oscillators or quartz crystals as a more reliable source of stable and precise clock frequency. While the use of an external oscillator circuit is simple but expensive and power-consuming, the much cheaper low-powered quartz crystals require way more attention.

There are many reasons why an external quartz crystal fails to start up or seems to fail. Some of them are hardware dependent, some are caused by improperly implemented startup code and some are caused by the way try to find them.

Hardware based quartz failures

Load capacitance

Each quartz is designed for a specific load link building service capacitance. In the normal setup that is used for devices with internal quartz support, two capacitors are needed from each pin of the quartz to ground. In the oscillation process, electric charge flows from one capacitor through the quartz into the other one and back again. So the attached capacitors need to match the quartz' internal capacitance for a stable and precise oscillation. Most manufacturers give a specific load capacitance in their datasheets, at which the quartz will oscillate with the specified frequency. It is important to note that, since the two attached capacitors are seen in series, their value needs to be twice the given load capacitance. So if a quartz is listed for a load of 16pF, two 32pF (or 33pF, as this is the closest standard value) need to be attached.

• If the load is too low, the quartz won't start oscillating, because not enough electric charge can swing back and forth and the quartz' internal ESR will dampen any upcoming oscillation.
• If the load is too high, the voltage swing of the oscillation is reduced because of the additional charge in the capacitors that cannot flow through the quartz. The driver circuit might fail to properly detect the oscillation.
• Between both failure points, the frequency of the oscillation is affected if the load differs from the required value.

Parasitic capacitances

While the attached capacitors form the main load for the quartz, there are other sources for an additional load that must be taken into consideration:

• Each processor pin forms a parasitic capacitance of ~1-2pF. If a socket is used, this value might greatly increase.
• The copper lines on the PCB may add several pF of parasitic capacitance. This can be reduced by keeping the lines to the quartz and the capacitors as short as possible and remove any lines (and most important: any ground plane) from the other PCB side below the quartz/capacitors/processor pins. The length of the two connections should match each other.
• some MSPs have internal capacitors, if using a 32.768kHz clock quartz (LFXT1 mode)

All these capacitances must be subtracted from the load capacitors' values to match the required load.

Software based quartz failures

Other reasons for a quartz failure

Usage of a debugger

On some devices, namely the MSP430F247 but maybe with others too, the Embedded Emulation Module (used for debugging) influences the clock outdoor fountains module. In a given case, the clock module kept reporting an oscillator fault with an attached XT2 quartz if the debugger was attached. In free-running mode, there was no problem. Further investigation revealed that with a debugger attached, OFIFG was flagged for XT1 even if the OSCOFF bit was set in SR. The startup code only checked OFIFG (which should be only affected by XT2 since XT1 was disabled with OSCOFF) and incorrectly detected a quartz failure. Checking the separate fault flags in the clock module revealed that XT2OF was clear and only LFXT1OF was set. When the source of the XT1 clock was redirected to the internal VLO, LFXT1OF remained clear and so did OFIFG.

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