# PLL Jitter on C28x Devices

From Texas Instruments Wiki

## Contents

# Introduction

The PLL jitter on C28x devices is not characterized. Therefore, a jitter value will not be found in the data manual. In cases where an estimate of PLL jitter is required, a design formula can be used. This article describes the formula and provides examples of its use.

Users of this formula should keep in mind that it is not characterized. TI does not test against this formula. It is, however, from the electrical specifications that the PLL was designed to.

# Formulas

The jitter formulas for different C28x based devices is given below.

### Formula 1

This formula applies to the following devices:

- F281x, C281x,
- F280x, F2801x, C280x
- F2833x, F2832x,
- Piccolo F2802x, F2803x, F2806x devices.

`MAX ( [input-clock-jitter], [pll_output_clock_period * 0.05 * sqrt(2)] )`

Notes:

- “input clock jitter” is specified in terms of absolute time.
- The "2" comes from the /2 after the PLL. this is typically enabled on C28x devices.

### Formula 2

This formula applies to the C2834x devices.

`MAX ( [input-clock-jitter], [pll_output_clock_period * 0.025 * sqrt(2)] )`

Notes:

- “input clock jitter” is specified in terms of absolute time.
- The "2" comes from the /2 after the PLL. this is typically enabled on C28x devices.

### Formula 3

This formula applies to the F28M35x devices.

`MAX ( [input-clock-jitter], [pll_output_clock_period * 0.05] )`

Notes:

- “input clock jitter” is specified in terms of absolute time.
- Note this is different than earlier devices: The 5% includes /2 divider jitter so the sqrt(2) is not needed.

# Examples

- Example 1
- Using formula 1
- Input clock frequency = 20 MHz + 5%
- PLL Output clock Frequency = 100 MHz
- SYSCLKOUT = (PLL Output/2) = 50 MHz

- This means:
- Input clock jitter = (1/20 MHz) * 0.05 = 2.5 ns
- [pll_output_clock_period * 0.05 * sqrt(2)] = (1/100 MHz) * .05 * sqrt(2) = 707 ps
- PLL Jitter = MAX (2.5 ns, 707 ps) = 2.5 ns

- This means:

- Example 2
- Using formula 1
- Input clock frequency = 20 MHz + 1%
- PLL output clock Frequency = 100 MHz
- SYSCLKOUT = (PLL Output/2) = 50Mhz

- This means:
- Input clock jitter = (1/20 MHz)*0.01 = 500 ps
- [pll_output_clock_period * 0.05 * sqrt(2)] = (1/100 MHz) * .05 * sqrt(2) = 707 ps
- PLL Jitter = MAX (500 ps, 707 ps) = 707 ps

- This means:

# XCLKOUT Jitter

- XCLKOUT is derived from SYSCLKOUT. Thus additional components in the design will also contribute to XCLKOUT jitter. How much jitter is a very difficult question to answer. The C2000 design team has attempted to estimate the jitter by taking into account the SYSCLKOUT -> XCLKOUT divider along with the path XCLKOUT takes through the device.

- The best answer we have is

- XCLKOUT jitter = (SYSCLK-jitter * SQRT (XCLKOUT_DIV)) + 1.6 ns

- This number is an estimate based on design information. It
**is not characterized based on actual silicon and therefore is not guaranteed**.