PRU-ICSS Feature Comparison

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Introduction

This article documents the feature differences between the PRU subsystems available on different TI processors.

Feature Comparison


PRU-ICSS Feature Comparison
Features AM18x AM335x AM437x AM570x AM571x AM572x K2G
PRUSS PRU-ICSS1 PRU-ICSS1 PRU-ICSS0 2x PRU-ICSS* 2x PRU-ICSS* 2x PRU-ICSS* 2x PRU-ICSS*
Number of PRU cores 2 2 2 2 2 2 2 2
Max Frequency CPU freq / 2 200 MHz 225 MHz ** 225 MHz ** 200 MHz 200 MHz 200 MHz 200 MHz
IRAM size (per PRU core) 4 KB 8 KB 12 KB 4 KB 12 KB 12 KB 12 KB 16 KB
DRAM size (per PRU core) 512 B 8 KB 8 KB 4 KB 8 KB 8 KB 8 KB 8 KB
Shared DRAM size 0 KB 12 KB 32 KB 0 KB 32KB 32KB 32KB 64KB w/ ECC
General Purpose Input    (per PRU core)                Direct                Direct; or 16-bit parallel capture; or 28-bit shift Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta
General Purpose Output   (per PRU core) Direct Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out
GPI Pins (PRU0, PRU1) 30, 30 17, 17 13, 0 20, 20 0/21***, 21/17 0/21***, 21/21 21, 21 20, 20
GPO Pins (PRU0, PRU1) 32, 32 16, 16 12, 0 20, 20 0/21***, 21/17 0/21***, 21/21 21, 21 20, 20
MPY/MAC N Y Y Y Y Y Y Y
Scratchpad N Y (3 banks) Y (3 banks) N Y (3 banks) Y (3 banks) Y (3 banks) Y (3 banks)
CRC16/32 0 0 2 2 2 2 2 **** 2
INTC 1 1 1 1 1 1 1 1
Peripherals n/a Y Y Y Y Y Y Y
     UART 0 1 1 1 1 / not pinned out ***** 1 1 1
     eCAP 0 1 1 not pinned out 1 / not pinned out ***** 1 1 1
     IEP 0 1 1 not pinned out 1 / not pinned out ***** 1 1 1
     MII_RT 0 2 2 not pinned out 2 2 2 2
     MDIO 0 1 1 not pinned out 1 1 1 1


* NOTE: The name PRU-ICSS and PRUSS are used interchangeably throughout the AM57xx and K2G documentation to describe the Programmable Real-Time Unit and Industrial Communication Subsystem.
** NOTE: The default frequency for AM437x is 200 MHz. However, the max frequency 225 MHz is achievable through Display PLL CLKOUT. Refer to the AM437x TRM for DSS limitations when configuring this PLL for frequencies >200 MHz.
*** NOTE: AM571x and AM570x PRU-ICSS1 does not pin out the PRU0 core GPIs/GPOs. The other AM571x and AM570x PRU cores (PRU-ICSS1 PRU1, PRU-ICSS2 PRU0, PRU-ICSS2 PRU1) each pin out the number of GPIs/GPOs listed in the table.
**** NOTE: AM572x SR1.1 does not have CRC16/32. Within the AM57x family, this feature is only available in AM572x SR2.0, AM571x, and AM570x.
***** NOTE: AM570x PRU-ICSS2 does not pin out these submodules. However, they are pinned out on the other AM570x subsystem (PRU-ICSS1).