PRU-ICSS Migration Guide: AM437x to AM57x

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Introduction

This article serves as a Software Migration Guide to assist in porting legacy software developed for the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) on AM437x to AM57x platforms. This guide will detail the PRU subsystem hardware differences and outline software modifications required for porting PRU firmware and ARM code to AM57x.

Refer to the PRU-ICSS chapter in the AM437x and AM572x/AM571x Technical Reference Manual for details about the PRU-ICSS on each device.

        NOTE:    The focus of this article is broad market support. Some industrial specific or ICSS features may be omitted.        

AM437x and AM57x Hardware Differences

This section provides an overview of the hardware differences between AM437x and AM57x. Both a high-level overview of the SoC-level hardware differences and a detailed overview of the PRU-ICSS hardware differences are included.

SoC-level Hardware Differences

AM437x and AM57x devices support different peripherals and features. The SoC memory map, peripheral register map, pinmuxing, ARM interrupt controller events, and eDMA mapping also differ between the devices.

Table 1 provides a quick comparison of the peripherals and features offered on AM437x and AM57x. For additional details, refer to the device-specific data sheets and user guides available at the device product pages:


Table 1. AM437x and AM57x Feature Comparison
Device Family AM437x AM572x AM571x
Device Family AM4376/7 - CortexA9  
AM4378/9 - CortexA9 with SGX530
AM5726 - 2x CortexA15, 2x C66x DSP 
AM5728 - 2x CortexA15, 2x C66x DSP with 2x SGX544
AM5716 - 1x CortexA15, 1x C66x DSP 
AM5718 - 1x CortexA15, 1x C66x DSP with 1x SGX544
Package Options    
Packages 491-pin BGA, .65-mm Ball Pitch with VCA 23 x 23mm, 0.8-mm Pitch, 760 Pin BGA (ABC)
Co-processors and Subsystems    
ARM Cortex-A Processor Cortex-A9 up to 1GHz;
32K-Byte Instruction and Data Caches;
256K-Byte L2 Cache or 256K-Byte L3 SRAM
2x Cortex-A15 up to 1.5GHz;
32K-Byte Instruction and Data Caches;
2M-Byte L2 Cache
1x Cortex-A15 up to 1.5GHz;
32K-Byte Instruction and Data Caches;
2M-Byte L2 Cache
Supported OPP: 50%/100%/120%/Turbo/Nitro Supported OPP: NOM, OD, HIGH
DSP Processor not present 2x C66x VLIW DSP up to 750MHz;
32K-Byte Instruction and Data Caches;
288K-Byte L2 Cache
1x C66x VLIW DSP up to 750MHz;
32K-Byte Instruction and Data Caches;
288K-Byte L2 Cache
ARM Cortex-M Processor available for General Purpose Use not present 1x Dual Cortex-M4 up to 213MHz;
32K-Byte Shared L1 Cache;
64K-Byte L2 RAM; 16K-Byte bootable L2 ROM
1x Dual Cortex-M4 up to 213MHz;
32K-Byte Shared L1 Cache;
64K-Byte L2 RAM; 16K-Byte bootable L2 ROM
Neon Co-processor Y Y
Graphics Engine SGX530 3D 2x SGX544 3D;
1x GC320 2D
1x SGX544 3D;
1x GC320 2D
System DMA eDMA eDMA, SDMA
PRU-ICSS 2 2
Memory Interfaces:    
mDDR/DDR2/DDR3 Controller Single 32-bit LPDDR2/DDR3L/DDR3 SDRAM Interface
Supports up to LPDDR2-533, DDR3-800, DDR3L-800, DDR3L-800
Total 2 GB Total Address Space
Dual 16/32-bit DDR3L/DDR3 SDRAM
Supports up to DDR3-1066
2 GB address space per EMIF (4 GB total)
Single 16/32-bit LPDDR2/DDR3L/DDR3 SDRAM
Supports up to DDR3-1333
Up to 4 GB across two chip selects
Dynamic Memory Manager (DMM) N Y
GPMC Y Y
ELM Y Y
SATA N Y
On Chip Memory (OCMC) 256KB (general purpose) 2.5MB 512KB
Security    
Crypto hardware accelerators Y Y
Video Interfaces:    
Camera ISP / VPFE Y N
Image and Video Accelerator N Y
Cortex-M4 Image Processing Unit (IPU) N 2
Video Input Port (VIP) N 3 1
Video Processing Engine (VPE) N Y
Camera Serial Interface (CSI) N N 2
Display Display Subsystem (DSS) Display Subsystem (DSS) N
Peripherals    
USB OTG Two (2) USB 2.0 High Speed ports with integrated PHY One (1) USB 3.0 Super Speed, Dual-Role-Device [DRD]
One (1) USB 2.0 High Speed, Dual-Role-Device [DRD] with integrated PHY
eMAC 2 (10/100/1000 Mbps) 2 (10/100/1000 Mbps)
CAN 2 2
McASP 2 (Both with 4 serializers) 8 (Two with 16 serializers, Six with 4 serializers)
UART 6 (all with IrDA) 10 (one with IrDA)
McSPI 5 4
QSPI 1 1
I2C 3 5
GPIO Up to 128 Up to 252 Up to 215
Keyboard Controller not present 1
eCAP 3 3
eHRPWM 6 3
eQPE 3 3
ADC 2 (1 TSC/ADC and 1 ADC) not present
PCIe not present 2
Removable Media    
MMC/SD/SDIO 3 4
D1W/HDQ Y Y
Power, Reset, and Clock Management    
RTC Y Y
Test Interfaces    
JTAG Y Y
ETM, PTM, & ETB ETM PTM
IEEE 1500 support Y N
RTT Y N
Misc    
GP Timer 12 16
Watchdog Timer 1 1


PRU-ICSS Hardware Differences between AM437x and AM57x

The table here compares the PRU-ICSS hardware between AM437x and AM57x. One primary difference is that AM437x has two instance of the PRU-ICSS that are not identical, while AM57x has two identical instances.

Below shows a comparison block diagram of the subsystems:

Figure 1. AM437x PRU-ICSS block diagram


Figure 2. AM57x PRU-ICSS block diagram

PRU-ICSS Memory Map Comparison

Local and Global Memory Maps

The AM57x PRU-ICSS local and global memory maps are backwards compatible with AM437x. However, the PRU-ICSS base address within the SoC memory map differs between devices. Table 2 compares these base addresses, which function as the starting address for the PRU-ICSS global memory map.

Table 2. PRU-ICSS Base Address Comparison for Global Memory Map
AM437x (PRU-ICSS1)
AM57x (PRU-ICSS1)
AM57x (PRU-ICSS2)
Start Address
 0x5440_0000  0x4B20_0000  0x4B28_0000



Note that on AM437x, the base address listed above corresponds to PRU-ICSS1. The PRU-ICSS0 memory map is accessed through the PRU-ICSS1 expansion port (address 0x5444_0000).

PRU-ICSS Submodules Register Content and Offsets

The register content and offsets of the following PRU-ICSS submodules are identical on AM437x and AM57x:

  • PRU-ICSS INTC
  • PRU-ICSS PRU<n> Control
  • PRU-ICSS PRU<n> Debug
  • PRU-ICSS UART
  • PRU-ICSS eCAP

The register content and offsets of the following PRU-ICSS submodules are partially backwards compatible for AM572x SR1.1 and fully backwards compatible for AM572x SR2.0 and AM571x:

Constants Table Differences

The PRU-ICSS constant table entries are partially backwards compatible.

Table 3. Constant Table Differences
Entry No. Value [31:0]
AM437x Function
AM57x Function
PRU-ICSS1 PRU-ICSS1 / PRU-ICSS2
0 0x0002_0000
PRU-ICSS INTC (local)
PRU-ICSS INTC (local)
1 0x4804_0000
DMTIMER2
Reserved
2 0x4802_A000
I2C1
Reserved
3 0x0003_0000
PRU-ICSS eCAP (local)
IRQ_CROSSBAR_21
(MAILBOX1_IRQ_USER0)
4 0x0002_6000
PRU-ICSS CFG (local)
PRU-ICSS CFG (local)
5 0x4806_0000
MMCHS 0
I2C3
6 0x4803_0000
MCSPI 0
Reserved
7 0x0002_8000
PRU-ICSS UART0 (local)
PRU-ICSS UART0 (local)
8 0x4600_0000
McASP0 DMA
McASP3 DAT
9 0x4A10_0000
GEMAC
Reserved
10 0x4831_8000
Reserved
Reserved
11 0x4802_2000
UART1
Reserved
12 0x4802_4000
UART2
Reserved
13 0x4831_0000
Reserved
Reserved
14 0x481C_C000
DCAN0
Reserved
15 0x481D_0000
DCAN1
Reserved
16 0x481A_0000
MCSPI 1
Reserved
17 0x4819_C0000
I2C2
Reserved
18 0x4830_0000
eHRPWM1/eCAP1/eQEP1
Reserved
19 0x4830_2000
eHRPWM2/eCAP2/eQEP2
Reserved
20 0x4830_4000
eHRPWM3/eCAP3/eQEP3
Reserved
21 0x0003_2400
Reserved
Reserved
22 0x480C_8000
Mailbox 0
Reserved
23 0x480C_A000
Spinlock
Reserved
24 0x0000_0n00, n = c24_blk_index[3:0]
PRU-ICSS PRU0/1 Data RAM (local)
PRU-ICSS PRU0/1 Data RAM (local)
25 0x0000_2n00, n = c25_blk_index[3:0]
PRU-ICSS PRU1/0 Data RAM (local)
PRU-ICSS PRU1/0 Data RAM (local)
26 0x0002_En00, n = c26_blk_index[3:0]
PRU-ICSS IEP (local)
PRU-ICSS IEP (local)
27 0x0003_2n00, n = c27_blk_index[3:0]
Reserved
Reserved
28 0x00nn_nn00, nnnn = c28_pointer[15:0]
PRU-ICSS Shared RAM (local)
PRU-ICSS Shared RAM (local)
29 0x49nn_nn00, nnnn = c29_pointer[15:0]
TPCC
OCMC_RAM2_CBUF
30 0x40nn_nn00, nnnn = c30_pointer[15:0]
L3 OCMC0
OCMC_RAM
31 0x80nn_nn00, nnnn = c31_pointer[15:0]
EMIF0 DDR Base
EMIF1_SDRAM_CS0


PRU Module Interface to PRU I/Os Differences

The functionality and structure of R30 and R31 is preserved on AM57x.

The supported GPI / GPO modes on AM571x are backwards compatible with AM437x. AM572x SR2.0/SR1.1 is partially backwards compatible. These devices do not support Sigma Delta or the 3 Channel Peripheral Interface (also used for EnDAT).

The number of PRU I/Os pinned out on each device differs, but the AM57x is backwards compatible with AM437x. The PRU-ICSS_Feature_Comparison table shows what I/Os are pinned out on each device.

Interrupt Controller Differences

The basic structure of the interrupt controller is the same in both devices. The basic INTC mapping of system events to channels to hosts is still the same. Both devices support the same number of total system events (64), channels (16), and hosts (10). However, on AM437, Host 7 within each PRU-ICSS is exported for signaling the other PRU-ICSS (instead of the ARM).

The INTC system events from modules inside the PRU-ICSS (i.e. System Event 0-31) are identical. The INTC system events from external sources (i.e. System Event 32-63) are not backwards compatible by default. However, AM57xx implements an Interrupt Controller Crossbar that provides flexibility in configuring the INTC system event source. At boot, the INTC can be configured to match the AM437x System Events. Table 3 shows which AM57xx IRQ_CROSSBAR events match the AM437x external system events.

The ARM interrupt numbers mapped to the PRU-ICSS source interrupts have also been updated on AM57x. See Table 4 for these changes.

Table 3. INTC Event Differences
Event
AM437x Function
AM57x Function
PRU-ICSS1 PRU-ICSS0 PRU-ICSS1 PRU-ICSS2
63
TPCC (EDMA) - tpcc_int_pend_po1
TPCC (EDMA) - tpcc_int_pend_po1
IRQ_CROSSBAR_361
(EDMA_TPCC_IRQ_REGION0)
IRQ_CROSSBAR_361
(EDMA_TPCC_IRQ_REGION0)
62
TPCC (EDMA) - tpcc_errint_pend_po
TPCC (EDMA) - tpcc_errint_pend_po
IRQ_CROSSBAR_359
(EDMA_TPCC_IRQ_ERR)
IRQ_CROSSBAR_359
(EDMA_TPCC_IRQ_ERR)
61
TPTC0 (EDMA) - tptc_erint_pend_po
TPTC0 (EDMA) - tptc_erint_pend_po
IRQ_CROSSBAR_370
(EDMA_TC0_IRQ_ERR)
IRQ_CROSSBAR_370
(EDMA_TC0_IRQ_ERR)
60
Mailbox0 - mail_u1_irq
Mailbox0 - mail_u1_irq
IRQ_CROSSBAR_21
(MAILBOX1_IRQ_USER0)
IRQ_CROSSBAR_21
(MAILBOX1_IRQ_USER0)
59
Mailbox0 - mail_u2_irq
Mailbox0 - mail_u2_irq
IRQ_CROSSBAR_135
(MAILBOX1_IRQ_USER1)
IRQ_CROSSBAR_135
(MAILBOX1_IRQ_USER1)
58
Debugss
Debugss
N/A
N/A
57
eHRPWM0-2 Trip Zone
eHRPWM3-5 Trip Zone
IRQ_CROSSBAR_204
(PWMSS1_IRQ_ePWM0_TZINT) *
N/A *
56
PRU-ICSS0 Host Interrupt 7
PRU-ICSS1 Host Interrupt 7
N/A
N/A
55
McASP0 Tx
McASP0 Tx
IRQ_CROSSBAR_104
(McASP1_IRQ_AXEVT)
IRQ_CROSSBAR_104
(McASP1_IRQ_AXEVT)
54
McASP0 Rx
McASP0 Rx
IRQ_CROSSBAR_103
(McASP1_IRQ_AREVT)
IRQ_CROSSBAR_103
(McASP1_IRQ_AREVT)
53
ADC_TSC
ADC_TSC
N/A
N/A
52
UART2
UART2
IRQ_CROSSBAR_69
(UART3_IRQ)
IRQ_CROSSBAR_69
(UART3_IRQ)
51
UART0
UART0
IRQ_CROSSBAR_67
(UART1_IRQ)
IRQ_CROSSBAR_67
(UART1_IRQ)
50
CPSW (c2_rx_thresh_pend)
CPSW (c2_rx_thresh_pend)
IRQ_CROSSBAR_334
(GMAC_SW_IRQ_RX_THRESH_PULSE)
IRQ_CROSSBAR_334
(GMAC_SW_IRQ_RX_THRESH_PULSE)
49
CPSW (c2_rx_pend)
CPSW (c2_rx_pend)
IRQ_CROSSBAR_335
(GMAC_SW_IRQ_RX_PULSE)
IRQ_CROSSBAR_335
(GMAC_SW_IRQ_RX_PULSE)
48
CPSW (c2_tx_pend)
CPSW (c2_tx_pend)
IRQ_CROSSBAR_336
(GMAC_SW_IRQ_TX_PULSE)
IRQ_CROSSBAR_336
(GMAC_SW_IRQ_TX_PULSE)
47
CPSW (c2_misc_pend)
CPSW (c2_misc_pend)
IRQ_CROSSBAR_337
(GMAC_SW_IRQ_MISC_PULSE)
IRQ_CROSSBAR_337
(GMAC_SW_IRQ_MISC_PULSE)
46
eHRPWM1
eHRPWM4
IRQ_CROSSBAR_208
(PWMSS2_IRQ_ePWM1INT)
N/A *
45
eQEP0
eQEP0
IRQ_CROSSBAR_210
(PWMSS1_IRQ_eQEP0INT)
IRQ_CROSSBAR_210
(PWMSS1_IRQ_eQEP0INT)
44
McSPI0
McSPI0
IRQ_CROSSBAR_60
(MCSPI1_IRQ)
IRQ_CROSSBAR_60
(MCSPI1_IRQ)
43
eHRPWM0
eHRPWM3
IRQ_CROSSBAR_207
(PWMSS1_IRQ_ePWM0INT)
N/A *
42
eCAP0
eCAP0
IRQ_CROSSBAR_213
(PWMSS1_IRQ_eCAP0INT)
IRQ_CROSSBAR_213
(PWMSS1_IRQ_eCAP0INT)
41
I2C0
I2C0
IRQ_CROSSBAR_51
(I2C1_IRQ)
IRQ_CROSSBAR_51
(I2C1_IRQ)
40
DCAN0 (dcan_intr)
DCAN0 (dcan_intr)
IRQ_CROSSBAR_222
(DCAN1_IRQ_INT0)
IRQ_CROSSBAR_222
(DCAN1_IRQ_INT0)
39
DCAN0 (dcan_int1)
DCAN0 (dcan_int1)
IRQ_CROSSBAR_223
(DCAN1_IRQ_INT1)
IRQ_CROSSBAR_223
(DCAN1_IRQ_INT1)
38
DCAN0 (dcan_uerr)
DCAN0 (dcan_uerr)
IRQ_CROSSBAR_224
(DCAN1_IRQ_PARITY)
IRQ_CROSSBAR_224
(DCAN1_IRQ_PARITY)
37
eHRPWM2
eHRPWM5
IRQ_CROSSBAR_209
(PWMSS3_IRQ_ePWM2INT)
N/A *
36
eCAP2
eCAP2
IRQ_CROSSBAR_215
(PWMSS3_IRQ_eCAP2INT)
IRQ_CROSSBAR_215
(PWMSS3_IRQ_eCAP2INT)
35
eCAP1
eCAP1
IRQ_CROSSBAR_214
(PWMSS2_IRQ_eCAP1INT)
IRQ_CROSSBAR_214
(PWMSS2_IRQ_eCAP1INT)
34
ADC1 (Mag Card)
ADC1 (Mag Card)
N/A
N/A
33
QSPI
QSPI
IRQ_CROSSBAR_363
(QSPI_IRQ)
IRQ_CROSSBAR_363
(QSPI_IRQ)
32
UART1
UART1
IRQ_CROSSBAR_68
(UART2_IRQ)
IRQ_CROSSBAR_68
(UART2_IRQ)


* Note that the AM437x PWM TZ event is associated with three PWM instances (PWM0-2), but the AM57xx event is only associated with one PWM instance. Also, AM437x supports 6 PWM instances, but AM57xx only supports 3.




Table 4. ARM Mapping of Source Interrupt to Event Number Comparison
Source
AM437x Event Number
AM57x Event Number
PRU-ICSS1 PRU-ICSS0 PRU-ICSS1 PRU-ICSS2
PRU_ICSS<k>_EVTOUT0
52
191
186
196
PRU_ICSS<k>_EVTOUT1
53
192
187
197
PRU_ICSS<k>_EVTOUT2
54
193
188
198
PRU_ICSS<k>_EVTOUT3
55
194
189
199
PRU_ICSS<k>_EVTOUT4
56
195
190
200
PRU_ICSS<k>_EVTOUT5
-
-
191
201
PRU_ICSS<k>_EVTOUT6
58
196
192
202
PRU_ICSS<k>_EVTOUT7
59
197
193
203

Peripheral Differences

PRU-ICSS UART

The PRU-ICSS UART is identical on AM437x and AM57x.

PRU-ICSS eCAP

The PRU-ICSS eCAP is identical on AM437x and AM57x. However, AM57x implements debug suspend for the PRU-ICSS eCAP. To run the PRU-ICSS eCAP during emulation suspend, the ECCTL1 register's FREE_SOFT bit will need to be configured.

PRU-ICSS Industrial Ethernet Peripheral (IEP)

The PRU-ICSS IEP is identical on AM437x, AM571x, and AM572x SR2.0, but partially backwards compatible on AM437x and AM572x SR1.1.

Compared to AM572x SR1.1, the AM437x IEP Timer supports more compare registers (16 on AM437x vs 8 on AM572x SR1.1) and adds support for a programmable reset value within the IEP_TMR_CNT_RST register

Instruction Set and Format Compatibility

The instruction set and format on AM57x is identical with AM437x.





Porting AM437x PRU Software to AM57x

The software changes required to port legacy code from AM437x to AM57x are based on the hardware differences between the two devices. This section details the key differences in software and describes how legacy code can be modified for AM57x PRU-ICSS. Note additional modifications may be required relating to other SoC differences that are external to the PRU-ICSS. Some of these modifications are discussed in the modifying software for SoC related differences section.

A checklist of changes required for both legacy PRU firmware and ARM code is provided below.

PRU Firmware Checklist
1
PRU addresses within global memory map
2
PRU INTC system event numbers
3
PRU Subsystem to PRU Subsystem interrupts
4
PRU IEP registers
5
PRU constant table values
6
SoC related changes (ie. peripheral addressing or registers, etc.)



ARM Code Checklist
1
PRU addresses within global memory map
2
PRU INTC system event numbers
3
SoC related changes (ie. peripheral addressing or registers, pinmux configuration, ARM Interrupt Controller, etc.)

Updating Global Memory Map References

When porting the legacy software to AM57x PRU-ICSS, the PRU-ICSS base address will need to be updated in both the PRU firmware and ARM code. Note most PRU firmware code should use the local memory map to reduce latencies and would not require any modification. Only firmware that accesses the global memory map requires updates.

No change is required for any offsets within the PRU-ICSS global memory map.

Configuring PRU INTC system events

AM57x implements an Interrupt Controller Crossbar that provides flexibility in configuring the INTC system event source. At boot, the PRU INTC can be configured to match the AM437x System Events. This pre-configuration step can be placed in the ARM or PRU code.

Updating PRU subsystem to PRU subsystem interrupts

AM437x has a dedicated host interrupt and system event for inter-PRU subsystem interrupts. For example, PRU-ICSS0 can interrupt PRU-ICSS1 by configuring the PRU INTC as follows:

PRU-ICSS0:
System Event [16-31] --> Channel x --> Host 7 (dedicated host interrupt)
PRU-ICSS1:
System Event 56 (dedicated system event) --> Channel x --> Host [0-1]

However, AM57xx does not have a dedicated host interrupt or system event. Therefore, inter-PRU subsystem interrupts should be generated similar to ARM to PRU interrupts. For example:

PRU-ICSS1:
Write to the PRU-ICSS2 INTC and manually set System Event [16-31]
PRU-ICSS2:
System Event [16-31] (dedicated system event) --> Channel x --> Host [0-1]

Updating PRU IEP Registers

For AM571x and AM572x SR2.0, the IEP Timer register offsets will need to be updated. (The 64-bit IEP Timer feature of these AM572x devices breaks register offset compatibility with AM437x's 32-bit IEP Timer.)

For AM572x SR1.1, no software change is required for the IEP Timer register offsets. However, code that uses compare registers 8-15 or the IEP_TMR_CNT_RST programmable reset will need to be updated, as these AM437x features are not supported.

Updating PRU Constant Table References

Differences in the PRU constant table will require changes to AM57x PRU firmware code.

The PRU constant table entries are partially backwards compatible, as some peripherals and features maintain the same entry numbers. However, other peripherals and features have been removed, added, or remapped to different entry numbers in the AM57x table.

Refer to the Constant Table Differences section for a comparison between the constant tables on both devices.

Modifying software for SoC related differences

AM437x and AM57x devices have additional differences at the SoC level that also require changes in both PRU firmware and ARM code. Below is a list of some key differences that require code updates. However, this is not an exhaustive list.

Key differences between AM437x and AM57x devices require PRU legacy code updates include:

1. Global device memory map
a. Start addresses of peripherals and features
b. Base addresses of modules
c. Register addresses and offsets
2. Peripherals
a. Refer to Table 1 in section 2 for peripherals supported on each device
b. Peripherals may have new memory or register maps. The functionality of registers may also change.
3. Pinmuxing