Programmable Realtime Unit Subsystem
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For the most up to date PRU-ICSS collateral click here
The Programmable Realtime Unit SubSystem (PRUSS) consists of:
- Two Programmable Realtime Units (PRU0 and PRU1) and their associated memories (data RAM and instruction RAM)
- An INTC (Interrupt Controller) for handling system input events. INTC also supports posting events back to the device level host CPUs (e.g. C674x DSP)
- SCR (Switched Central Resource) for connecting the various internal and external masters to the resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can also work in coordination with device level host CPUs. This is determined by the nature of the program which is loaded into the PRU's instruction memory. Several different signaling mechanisms are available between the two PRUs and the device level host CPUs.
The PRU subsystem is supported on OMAP-L1x8/C674m/AM18xx devices (where m is an even number). A block diagram of the PRUSS is shown below.
- Provides 2 Independent Programmable Realtime Unit Cores
- 32-Bit Load/Store RISC architecture
- 4K Byte instruction RAM per core
- 512 Bytes data RAM per core
- PRUSS can be disabled via software to save power
- Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores.
- PRU intended operation is little endian similar to ARM and DSP processors.
- Provides standard power management mechanism
- Clock gating provided
- Entire subsystem under a single PSC clock gating domain
- Provides interrupt controller
- Provides switched central resource
PRU Subsystem Training Material
These slides contain a nice overview of the PRU Subsystem. This material is a recommended starting point for those who have never used the PRU Subsystem. Note that the material in the slides is accurate as of the time it was posted, but the associated pages of the wiki will always contain the most up-to-date information.
PRU Subsystem Hardware Documentation
- PRU Subsystem Memory Map
- PRU Core Execution Unit
- PRU Interrupt Controller
- PRUSS Differences between OMAPL1x8/AM18x and OMAP1x7/AM17x
PRU Subsystem Software Development
Information on developing software for the PRUs can be found here.