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Programming PLL Controllers on OMAP-L1x7/C674x/AM17xx/DA8xx

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This article applies to the following device family

Download

Download the spreadsheet: OMAPL1x7/C674x/AM17xx/DA83xx Clocking Spreadsheet.

Background

There is one PLL controller on this family of devices. This PLL controller has multiple output clocks and several configurations.  The clock outputs of the PLL controllers are used to clock different parts of the device including the ARM, DSP, DDR2 controller, and device peripherals.  Furthermore, each input and ouput clock has a frequency min and max that must be observed.  Some of these frequency limits change with the operating voltage of the device.

Clocking Check Spreadsheet

The clocking check spreadsheet was created such that a user can quickly check for timing violations.  The spreadsheet was created based on the PLL controller information in the OMAP-L137, C6747, AM1707, DA830 device data manual (see image below).  A user can enter several values including PLL multipliers and system clock dividers. The spreadsheet will flag any timing violations.  The user can also specify the operating core voltage of the device.  The spreadsheet will adjust the frequency limits based on the operating voltage.

OMAPL137 C6747 PLL Topology.JPG

Spreadsheet Improvements

The spreadsheet was created with minimal functionality.  Suggestions for future improvements include:

  • NOTE: The PLL calculator spreadsheet shows violations for "super-set" devices in the family that support the maximum frequency. It is recommended to cross-check with the device specific datasheet for max frequency supported if you are using a lower speed grade or subset device in this processor family.
  • Add clocking checks for device peripherals.

References