Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx

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Check out the new PLL, System and Peripheral Clock Calculation spreadsheet
Download the spreadsheet for OMAP-L138/L132, C6748/6/2 and AM18x devices
Download the spreadsheet for OMAP-L137, C6747/5/3 and AM17x devices

Archived old spreadsheet: OMAPL138_C6748_Clocking_Spreadsheet.


There are two PLL controllers on OMAP-L1x8, C674x, and AM18xx devices. Each PLL controller has multiple output clocks and several configurations.  The clock outputs of the PLL controllers are used to clock different parts of the device including the ARM, DSP, DDR2 controller, and device peripherals.  Furthermore, each input and ouput clock has a frequency min and max that must be observed.  Some of these frequency limits change with the operating voltage of the device.

Clocking Check Spreadsheet

The clocking check spreadsheet was created such that a user can quickly check for frequency violations.  The spreadsheet was created based on the PLL controller information in the OMAP-L138, C6748, AM1808 device data manual (see image below).  A user can enter several values including PLL multipliers and system clock dividers. The spreadsheet will flag any timing violations.  The user can also specify the operating core voltage of the device.  The spreadsheet will adjust the frequency limits based on the operating voltage.

OMAPL138 C6748 PLL Topology.JPG

Spreadsheet Improvements

The spreadsheet was created with minimal functionality.  Suggestions for future improvements include:

  • Add clocking checks for device peripherals.