Reconfiguring EDMA channel allocation on ARM

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1 How to map different EDMA3 resources (DMA channels, QDMA channels, TCCs, PaRAM Sets) on ARM side (region 0)
2 How to change various other global settings on DM6467
- 2.1 How to change default event queue (or Transfer Controller, TC) priorities?
3 Present configuration of EDMA3 resources on DaVinci platforms:

How to map different EDMA3 resources (DMA channels, QDMA channels, TCCs, PaRAM Sets) on ARM side (region 0)

DMA Channels

In the source file arch\arm\mach-davinci\dma.c, array dm646x_edma_channels_arm[] is used to map various DMA channels to ARM side shadow region. The two 32-bit words (and hence 64 bits) correspond to the 64 DMA channels available on DaVinci-HD. Bits 0-31 of the first word correspond to first 32 (i.e. 0-31) DMA channels whereas bits 0-31 of the second word correspond to next 32 (i.e. 32-63) DMA channels. See the code snippet below:

static unsigned int dm646x_edma_channels_arm[EDMA_NUM_DMA_CHAN_DWRDS] = {
    0x30FF1FF0u,  0x00C007FFu
};

'1' for a particular bit means that the corresponding DMA channel is available to ARM side users and could be allocated to one of them, if requested. '0' means the channel is NOT available to the ARM side users and hence could be used by other masters (for e.g. DSP).

To map/un-map the DMA channels to ARM side region, one has to modify this array accordingly, such that the same DMA channel(s) should NOT be used by other masters in the whole system. All masters should work upon ONLY their subset of resources. In case of a conflict (different masters working on same set of resources), the system behavior is unpredictable.

QDMA Channels

In the source file arch\arm\mach-davinci\dma.c, array dm646x_qdma_channels_arm[] is used to map various QDMA channels to ARM side shadow region. Bits 0-7 of the single 32-bit word of this array correspond to the 8 QDMA channels available on DaVinci-HD. Bit 0 corresponds to first QDMA channel, bit 1 corresponds to second QDMA channel and so on. See the code snippet below:

static unsigned char dm646x_qdma_channels_arm[EDMA_NUM_QDMA_CHAN_DWRDS] = {
    0x00000080
};

'1' for a particular bit means that the corresponding QDMA channel is available to ARM side users and could be allocated to one of them, if requested. '0' means the channel is NOT available to the ARM side users and hence could be used by other masters (for e.g. DSP).

To map/un-map the QDMA channels to ARM side region, one has to modify this array accordingly, such that the same QDMA channel(s) should NOT be used by other masters in the whole system. All masters should work upon ONLY their subset of resources. In case of a conflict (different masters working on same set of resources), the system behavior is unpredictable.

TCCs (i.e Interrupt channels)

In the source file arch\arm\mach-davinci\dma.c, array dm646x_tcc_arm[] is used to map various TCCs to ARM side shadow region. The two 32-bit words (and hence 64 bits) correspond to the 64 TCCs available on DaVinci-HD. Bits 0-31 of the first word correspond to first 32 (i.e. 0-31) TCCs whereas bits 0-31 of the second word correspond to next 32 (i.e. 32-63) TCCs. See the code snippet below:

static unsigned int dm646x_tcc_arm[EDMA_NUM_DMA_CHAN_DWRDS] = {
	0x30FF1FF0u, 0x00C007FFu
};

'1' for a particular bit means that the corresponding TCC is available to ARM side users and could be allocated to one of them, if requested. '0' means the TCC is NOT available to the ARM side users and hence could be used by other masters (for e.g. DSP).

To map/un-map the TCCs to ARM side region, one has to modify this array accordingly, such that the same TCC(s) should NOT be used by other masters in the whole system. All masters should work upon ONLY their subset of resources. In case of a conflict (different masters working on same set of resources), the system behavior is unpredictable.

In general, same set of DMA channels and TCCs are allocated to ARM side users.

PaRAM Sets

In the source file arch\arm\mach-davinci\dma.c, array dm646x_param_entry_arm[] is used to map various PaRAM Sets to ARM side shadow region. The 16 32-bit words (and hence 512 bits) correspond to the 512 PaRAM Sets available on DaVinci-HD. Bits 0-31 of the first word correspond to first 32 (i.e. 0-31) PaRAM Sets, bits 0-31 of the second word correspond to next 32 (i.e. 32-63) PaRAM Sets and so on. See the code snippet below:

static unsigned int dm646x_param_entry_arm[] = {
	0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
	0x0u, 0x0u, 0x0u, 0x0u,
	0x0u, 0x0u, 0x0u, 0x0u,
	0x0u, 0x0u, 0x0u, 0x0u
};

'1' for a particular bit means that the corresponding PaRAM Set is available to ARM side users and could be allocated to one of them, if requested. '0' means the PaRAM Set is NOT available to the ARM side users and hence could be used by other masters (for e.g. DSP).

To map/un-map the PaRAM Sets to ARM side region, one has to modify this array accordingly, such that the same PaRAM Set(s) should NOT be used by other masters in the whole system. All masters should work upon ONLY their subset of resources. In case of a conflict (different masters working on same set of resources), the system behavior is unpredictable.

Note 1: DMA channels and PaRAM Sets are one-to-one mapped, meaning thereby DMA channel X can ONLY use PaRAM Set X for its working. The system integrator should make sure that the DMA channels mapped to ARM side should also have the corresponding PaRAM Sets (at least) mapped to ARM side. Other PaRAM Sets available on the ARM side (lying between 64-511) could be used for link purpose. So they can be independently mapped/unmapped to ARM side.

Note 2: A DMA/QDMA channel also require a TCC for correct functioning. By default, DMA channels and TCCs are one-to-one mapped, meaning thereby DMA channel Y can ONLY use TCC Y for its working. (No such constraint is there for QDMA channels.) The system integrator should make sure that the DMA channels mapped to ARM side should also have the corresponding TCCs (at least) mapped to ARM side. In case user passes a specific TCC to be used by the DMA/QDMA channel, he/she should first check its availability on ARM side.

Note 3: Same methodology can also be used to map different EDMA3 resources on ARM side on the DaVinci platform.

How to change various other global settings on DM6467

How to change default event queue (or Transfer Controller, TC) priorities?

Array dm646x_queue_priority_mapping[] can be used to change the default event queue priorities. This array is an array of structures having the first structure member as the event queue number and the second structure member as the priority. '0' is the highest priority, '1' is the second highest and so on. See the code snippet below:

static struct edma_map dm646x_queue_priority_mapping[EDMA_DM646X_NUM_EVQUE] = {
	/* {Event Queue No, Priority} */
	{0, 0},
	{1, 1},
	{2, 2},
	{3, 3}
};

The system integrator can appropriately modify this array, keeping bandwidth limitations (for different users and whole system in general) in mind.

Present configuration of EDMA3 resources on DaVinci platforms:

EDMA3 Resource	DM644X		DM646X
EDMA3 Resource	ARM	DSP	ARM	DSP
DMA Channel	0-63	None	4-12,16-23,28,29,32-42,54,55	0-3,13-15,24-27,30,31,43-53,56-63
QDMA Channel	4	0-3,5-7	7	0-6
TCC	0-63	None	4-12,16-23,28,29,32-42,54,55	0-3,13-15,24-27,30,31,43-53,56-63
PaRAM Set	0-127	None	0-127	128-511

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