A universal asynchronous receiver/transmitter, abbreviated UART, is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or RS-485. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. UART generally has FIFO buffers that assist in transmission and reception of data. Multiple bytes can be written to the transmit FIFO in a single turn by the processor and the UART transmits these bytes one bit at a time. Similarly, the UART can interrupt the processor once a sizeable number of bytes are received by the UART and stored in the receiver FIFO. Presence of FIFOs improve the software performance of the application. Usually the Transmit FIFOs and Receiver FIFOs have configurable threshold levels on attaining which they interrupt the processor.
The UART/IrDA/CIR IP also supports Infrared Data Association (IrDA) and Consumer Infrared (CIR) operational modes along with the general UART mode. IrDA defines physical specifications communications protocol standards for the short-range exchange of data over infrared light, for uses such as personal area networks (PANs). CIR, refers to devices employing the infrared electromagnetic spectrum for wireless communication. One of the popular application of CIR is in Television Remote Controls for communication with the Television set. IrDA and CIR transceivers shall be present in the UART/IrDA/CIR controller and shall use the same FIFO as that of UART mode to communicate with the external transmitter/receiver.
- Firstly, configure the system clocks for UART instance using the function provided in the platform directory.
- Perform Pin Multiplexing for the UART instance.
- Invoke the API UARTModuleReset() to perform a module reset of the UART instance.
- If the UART is to be configured in FIFO mode, use the API UARTFIFOConfig() to perform FIFO configurations.
- The specified baud rate of communication is achieved by appropriately programming the Divisor Latch registers. Specifically, the divisor value is a function of the Operating frequency and the desired baud rate. The computation formula for the divisor latch value also differs based on the operating mode specified. Use the API UARTDivisorValCompute() to compute the divisor value that is to be programmed to the Divisor Latch registers.
- Invoke the API UARTDivisorLatchWrite() to program the computed divisor value to the divisor latch registers.
- Switch to Register Configuration Mode B using the API UARTRegConfigModeEnable() passing appropriate parameters.
- Configure the Line Characteristics using the API UARTLineCharacConfig() passing appropriate parameters.
- Disable access to the divisor latch registers using the API UARTDivisorLatchDisable().
- Ensure that the Break condition is disabled using the API UARTBreakCtl() passing appropriate parameters.
- Call the API UARTOperatingModeSelect() with appropriate parameters to switch the UART to 16x operating mode.
- Configure the ARM interrupt controller to generate UART interrupt by registering the UART ISR.
- Enable required UART interrupts using the API UARTIntEnable() passing appropriate parameters.
- Configure the functional clocks of EDMA using the function EDMAModuleClkConfig(). Similarly, configure the functional clocks of UART0 instance using the function UART0ModuleClkConfig().
- Perform Pin Multiplexing for the required UART instance using the function UARTPinMuxSetup() passing appropriate instance number.
- Initialize the EDMA3 instance using the API EDMA3Init() passing the appropriate event queue number to be used, as an argument.
- Perform the configurations to handle interrupts:
- Enable IRQ bit in CPSR register of ARM processor using the API IntMasterIRQEnable(). This enables ARM to receive interrupt requests over IRQ line.
- Initialize the Interrupt Controller (INTC) using the API IntAINTCInit().
- The ISRs (Interrupt Service Routine) of EDMA3 Completion interrupt and EDMA3 Error interrupt have to be registered in the INTC. This is done using the API IntRegister() passing appropriate arguments.
- Set the priority for the above interrupts using the API IntPrioritySet() passing appropriate parameters.
- Enable the INTC to receive the above interrupts using the API IntSystemEnable() passing appropriate arguments.
- Now the UART instance has to be initialized to appropriate settings for proper operation and communication. The initialization sequence used remains the same as that followed for operating UART in interrupt mode. As an addition, the API UARTDMAEnable() needs to be invoked to enable appropriate DMA mode of operation for the UART.
- EDMA3 communicates with other peripherals through logical channels. A logical channel each is required for UART TX Event and UART RX Event for these events to get serviced when they occur.
- Individually set the PaRAM set entries for UART Transmit and Receive DMA channels using the API EDMA3SetPaRAM() passing appropriate parameters.
- Start EDMA transfer on the required channels using the API EDMA3EnableTransfer() passing appropriate parameters.
- As mentioned above, two ISRs are used – EDMA3 Completion ISR and EDMA3 Error ISR. EDMA3 generates a completion interrupt when the count values (A, B and C) of the PaRAM set are depleted to zero. EDMA3 generates an error interrupt when EDMA could not service an event it received.
- These ISRs have code which usually clears certain bits in relevant registers of EDMA3 register set.
- Further, a callback function is usually written which is invoked from ISR. This function does operations specific to the channels. For example, disabling transfer over the specified EDMA channel.
Note: In the UART EDMA application present at examples/evmAM335x/uart_edma/src/, a Dummy transfer concept is used. The UART Transmit PaRAM set is linked to a Dummy PaRAM set. A Dummy PaRAM set is defined as one where at least one of the count fields (A, B or C) is and at least one of them is non-zero. The scenario of its use is explained below. UART generates a transmit event to the EDMA whenever its Transmit Holding Register(THR)/TX FIFO becomes empty. The EDMA then transfers the configured number of bytes to the THR/TX FIFO. On the last transaction, EDMA again transfers the requisite number of bytes and its count fields are depleted to zero. UART transfers these bytes and again generates an event to EDMA. If a Dummy PaRAM set is linked to the TX PaRAM set, the EDMA services the Dummy PaRAM set before raising a completion interrupt to the ARM processor. In the absence of this Dummy PaRAM set, EDMA registers a missed event and raises an error interrupt to the ARM.