TCI6616/C6670/TCI6608/C6678/TCI6618 Device simulator User Guide

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Purpose

The purpose of this document is to walk the user through the various aspects of TCI6616/C6670/TCI6608/C6678/TCI6618/C6657 device simulators, available with Code Composer Studio. This includes:

  • Overview
  • Simulator Configurations
  • Installing the Simulator
  • Details of the models that constitute the simulator


Simulator Configurations

Based on the modeling-abstraction level (details modeled in the simulation), the TCI6616/C6670/TCI6608/C6678/TCI6618/C6657 Device simulators are classified as

  • Functional simulator configuration
  • Cycle Approximate (CX) simulator configuration
Device simulator categorized based on different abstraction level
Configuration Scope

Key Benefits



Functional Simulator
  • Functional and Bit-accurate
  • Model the functionality of CPU, cache, DMA, co-proc and peripherals
  • Model the device memory map.
  • The application binary run on simulator can be run on Hardware and vice-versa
  • Faster Platform (than RTL and pre-si hardware emulators)
  • Whole application system creation; OS, device driver support
Cycle Approximate (CX) simulator
  • Cycle Accurate and Bit Accurate
  • Application performance measurement and tuning


The following is the list of device simulator configuration supported

TCI6616

  1. TCI6616 Functional Device simulator configuration, Little Endian
  2. TCI6616 Functional Device simulator configuration, Big Endian
  3. TCI6616 Cycle Approximate Device simulator configuration, Little Endian
  4. TCI6616 Cycle Approximate Device simulator configuration, Big Endian

C6670

  1. C6670 Functional Device simulator configuration, Little Endian
  2. C6670 Functional Device simulator configuration, Big Endian
  3. C6670 Cycle Approximate Device simulator configuration, Little Endian
  4. C6670 Cycle Approximate Device simulator configuration, Big Endian

TCI6608

  1. TCI6608 Functional Device simulator configuration, Little Endian
  2. TCI6608 Functional Device simulator configuration, Big Endian
  3. TCI6608 Cycle Approximate Device simulator configuration, Little Endian
  4. TCI6608 Cycle Approximate Device simulator configuration, Big Endian

C6678

  1. C6678 Functional Device simulator configuration, Little Endian
  2. C6678 Functional Device simulator configuration, Big Endian
  3. C6678 Cycle Approximate Device simulator configuration, Little Endian
  4. C6678 Cycle Approximate Device simulator configuration, Big Endian

TCI6618

  1. TCI6618 Functional Device simulator configuration, Little Endian
  2. TCI6618 Functional Device simulator configuration, Big Endian
  3. TCI6618 Cycle Approximate Device simulator configuration, Little Endian
  4. TCI6618 Cycle Approximate Device simulator configuration, Big Endian

C6657

  1. C6657 Functional Device simulator configuration, Little Endian
  2. C6657 Functional Device simulator configuration, Big Endian



Simulator installation

Prerequisite

  • Win XP
  • Code Composer™ Studio
  1. Code Composer™ Studio v5, or a later version preferred.
  • Note: Needed only in case of using Virtualized IO feature to stream Layer 2 Ethernet packet to/from your m/c ethernet socket

Preferred machine configuration

  • 2.4 GHz processor or above
  • 2GB Memory or above

Release Package and installation

  • The simulator release is available as self-extracting installer.
Note: While installing this simulator release on
  • CCS v5 installation, select the Code Composer Studio™ installation path(<CCSv5.x_install_path>\ccsv5\ccs_base_5.x.x.xxxxx\) when the installer prompts for simulation installation path.

Simulator Selection & Configuration

Functional simulator Selection & Configuration

  • Bring up CCS & click on Target->New Target Configuration
  • Specify the target configuration file name & use shared location or store it in the project folder.
Snap1.JPG

  • Target selection will appear. Select connection type as Texas Instruments Simulator & type the device you are interested in the device filter window (e.g. TCI6606)
  • Select appropriate simulator configuration from the filtered list and press the Save buttont to save the configuration.
Snap2.JPG

Cycle Approximate simulator Selection & Configuration

  • The steps for configuring the Cycle Approximate simulator is same as the Functional simulator configuration, except before saving the configuration you are expected to select the appropriate DDR memory configuration
  • Click on the 'Target configuration' to setup the DDR configuarion
Snap2 2.JPG
  • Click on any one of the DSP name under the All Connection window.(step 1, as highlighted in the diagram below)
  • This will display a list of configuration which also includes the DDR configuration. Select the desired DDR configuration (step 2, as highlighted in the diagram below) and click on Save button (step 3 as highlighted in the diagram below) to save this configuration
Snap3.JPG




Simulation Features


  • CIO, Breakpoints, register, memory windows
  • Synchronous and Asynchronous execution of cores
  • Global and local breakpoints
  • Advanced debug capabilities
  • Code Coverage,, Cache Tag RAM view, Multi-level memory hierarchy visibility,
  • Analysis capabilities
  • Function profiling with interrupt awareness
  • Code coverage, Cache & device events
  • EMAC and SRIO IO virtualization
  • UART connectivity to TCP/IP terminal


Device simulator -- IP model details


IP Block
TCI6616
C6670
TCI6608
C6678
TCI6618 C6657
CPU 4 C66x 4 C66x 8 C66x 8 C66x 4 C66x 2 C66x
CorePac Yes Yes Yes Yes Yes Yes
RSA Yes Yes NA NA Yes NA
MSMC Yes Yes Yes Yes Yes Yes
DDR3 EMIF Yes Yes Yes Yes Yes Yes
Debug & Trace No No No No No No
Boot ROM No No No No No No
Semaphore Yes Yes Yes Yes Yes Yes
Power Management
     PSC Registers No No No No No Yes
Device State control Register
     Inter process communication registers Yes Yes Yes Yes Yes Yes
     Others No No No No No No
PLL No No No No No No
EDMA Yes Yes Yes Yes Yes Yes
RAC Yes Yes NA NA Yes NA
TAC Yes Yes NA NA Yes NA
VCP2 Yes Yes NA NA Yes Yes
TCP3d Yes Yes NA NA Yes Yes
TCP3e Yes Yes NA NA Yes NA
FFTC Yes Yes NA NA Yes NA
Multi-core Navigator
     Queue Manager Yes Yes Yes Yes Yes Yes
     Packet DMA Yes Yes Yes Yes Yes Yes
I2C No No No No No No
PCIe Yes Yes Yes Yes Yes Yes
UART No No No No No Yes
SPI No No No No No No
AIF2 Yes Yes Yes Yes Yes No
SRIO Yes Yes Yes Yes Yes Yes
Network Co-processor
    Ethernet Switch Yes Yes Yes Yes Yes Yes
    Packet Accelerator Yes Yes Yes Yes Yes Yes
    Security Accelerator Yes Yes Yes Yes Yes Yes
Hyperlink No No No No No No
BCP NA NA NA NA Yes Yes
GPIO NA NA NA NA NA Yes
TIMER64 Yes Yes Yes Yes Yes Yes
INTC Yes Yes Yes Yes Yes Yes


The following pictures summarizes the sections that are modeled/not-modeled in TCI6616, TCI6608, TCI6618 and C6657 simulator configurations.

TCI6616 simulator scope.jpg


C6678 simulator scope.jpg


Tci6618_sim.jpg


C6657_Simulator.jpg


Cycle Accuracy of Simulator

The following table summarizes the different category of models, classified based on the degree/details of accuracy models, and the IP models in the Device Cycle Approximate simulator configuration that are modeled for it.
IP Model Category

Accuracy w.r.t RTL
IP Models in TCI6616/C6670/TCI6608/C6678/TCI6618 Devices
Cat3: Programmers-view (PV) model
  • No Accuracy.


NA
  • SRIO, GPIO,
  • INTC,
  • VCP2, TAC, RAC,
  • Queue Manager
  • RSA
  • Boot ROM
  • Network Co-processor
  • IPC, Semaphore,
Cat2: PV with Timing (PVT) models
  • Computation-time-accurate models


>75%
  • PKTDMA,
  • TCP3D, TCP3E,
  • FFTC
Cat1: Highly cycle-accurate models
  • Arbitration, Priority and pipelines are modeled to match the micro-arch details


>90%
  • C66x ISA,
  • CorePac Memory System (L1+L2),
  • MSMC, DDR-EMIF,
  • EDMAv3, Timer
  • AIF2 Timer module
Cat0: RTL-to-C converted models
100%
None



Cycle Approximate Simulator bus-topology details.

Since the IP models in the Device Cycle accurate simulator are modeled at different abstraction level (as summarized in the table above), the simulator bus-topology uses a mix of interconnect as depicted in the following diagram

Keystone topology.jpg
 


Cycle Accuracy Validation Process

The cycle accuracy is measured and calibrated against the RTL/Silicon w.r.t a set of identified benchmarks/test-cases

Accuracy Validation process.JPG

Cycle Accuracy Results

The following table summarizes the cycle accuracy acheived on the Cycle Approximate simulator configuration.

Scenarios/Paths

Achieved Cycle Accuracy
CPU w/ 100% L1D and L1P Cache/SRAM
100%
CPU w/ accesses within L2 Cache controller
95%
CPU w/ accesses to MSMC
90%
CPU w/ accesses to DDR
80%
EDMA transfers involving internal, shared and external memories
80%




Virtualized IO

The TCI6616/C6670/TCI6608/C6678/TCI6618 Device simulator supports Virtualized IO capabilitied for the following IP models.
  1. SRIO
  2. Ethernet Switch

SRIO Message Passing Support

  • SRIO Type 11 messages encapsulated in TCP headers can be passed into and out of the simulator
  • SRIO physical layer is not modeled
  • Dedicated port routes TCP packets to a socket in the simulator that strips the TCP header and forwards the SRIO message to the SRIO port 0
  • User’s application on PC produces and consumes SRIO messages tunneled over TCP
  • TCI6616/C6670/TCI6608/C6678/TCI6618 Device Simulator SRIO Model User Guide contains configuration details and packet structure
Srio io.JPG


Simulator Ethernet Connectivity

  • The EMAC Model in the Device simulator supports Layer 2 (Data Link Layer) messaging over the network.
  • Ethernet packet transmission and reception
  • It uses the WinPCAP library to interact with the network. The EMAC will capture Ethernet packets based on the MAC address configured in the simulator configuration file.
  • Broadcast packets are also forwarded to the simulator.
  • Details contained in Device Simulator EMAC Model User Guide.
Ethernet packet processing.jpg




IP Model Details

C66x ISA

What is Supported? What is not Supported?
  • C66x ISA
  • Interrupts and Exceptions

Note: It is recommeded to use Cycle approximate simulator configuration for benchmarking purposes because the functional simulator does not support CPU cross-path stalls.

 

C66x CorePac

What is Supported? What is not Supported?
  • L1/L2 Cache controller
  • Interrupt Selector, IDMA
  • Extended Memory Controller
  • Cache and memory simulator statistics
  • Clock Speed: C66x CorePac runs at
    1 GHz Clock
  • The following bits in the MAR registers, and its associated
    functionality is not supported
  • WTE bit – selects
    between write-back (0)
    and write-through (1)
    caches in
    DMC/PMC/UMC
  • PCX bit – disables (0)
    and enables (1) caching
    in MSMC RAM (not
    committed)
  • PFX bit – disables (0) and
    enables (1) prefetching in
    XMC.
  • XMC
  • XMC registers
  • Address translation
    functionality at XMC is
    not supported
  • Memory protection
    functionality


 

RSA

What is supported? What is not supported?
  • RSA functionality


Multi-core Shared Memory controller (MSMC)

What is Supported? What is not Supported?
  • MSMC RAM
  • MSMC registers
  • Address translation functionality
    at MSMC*
  • 36-bit addressing mode*
  • CFGLCKSTAT and
    CFGLCK register
    functionality

 *Supported on functional simulator configurations only

 

EMIFv4 - DDR3

What is supported?
  • The following DDR memories are supported(selectable before the simulation starts)
  • DDR3 - 1333
  • DDR3 - 1600 

The timing parameters used for these memories are listed in the table below.

Description DDR-1600 DDR-1333
SDRAM burst length(in bytes)
8 8
Number of internal banks 8 8
Depth of command FIFO
16 16
Depth of read response fifo
22 22
Depth of write response
7 7
Depth of write data fifo
24 24
Data bus width between EMIF4 and memory(in bits)
64 32
System Interface data bus-width (in bits) 256 256
Page Size(in KB)
2048 2048
Memory clock period (in picoseconds) 1250 1500
EMIF Phy latency 3 3
SDRAM refresh period in number of memory clock cycles 6250 6250
SDRAM size in MB 256 256

Minimum number of mem_clk cycles from activate to precharge - 1

(t_ras)

28 28

Minimum number of mem_clk cycles from activate to activate - 1

(t_rc)

38 38

Minimum number of mem_clk cycles from refresh/load_mode to refresh or activate - 1

(t_rfc)

88 88

Minimum number of mem_clk cycles from precharge to refresh/activate - 1

(t_rp)

10 10

Minimum number of mem_clk cycles from activate to activate to a different bank - 1

(t_rrd)

6 6

Minimum number of mem_clk cycles from the last read command to precharge - 1

(t_rtp)

6 6

Minimum number of mem_clk cycles from last write transfer to precharge - 1

(t_wr)

12 12

Minimum number of mem_clk cycles from last write to read - 1

(t_wr)

6 6
CAS latency (cl)
10 9
Write latency(wl) 8 7
Synchronizer latency 3 3
(t_ccd)
4 4
Minimum number of mem_clk cycles from activate to read/write - 1 10 10
Threshold to do back2back writes before reads 5 5
Threshold to do back2back writes before reads 3 3
What is not supported?
  • EMIFv4 MMR
  • 36-bit addressing

Semaphore

What is supported? What is not supported?
  • 32 independent semaphores.
  • Direct, Indirect and combined mode for semaphore acquisition.
  • Queued requests for used semaphores
  • Semaphore access grant interrupt for queued request
  • Allows the application to check the status of semaphores.
  • Error detection and interrupts



PSC

What is supported? What is not supported?
* PSC Register Only Model * Power/Module enabling bit toggles


Device Status Control Register

Inter Processor Communication
What is Supported? What is not Supported?
  • IPC registers and associated functionality
  • Interrupt output capability to an external host via device pin
    (HOUT)


Others
What is supported?
What is not supported?

  • JTAGID
  • DEVSTAT
  • KICK0, KICK1
  • DSP_BOOT_ADDRx
  • MACID
  • LRSTNMIPINSTAT_CLR
  • RESET_STAT_CLR
  • BOOTCOMPLETE
  • RESET_STAT
  • LRSTNMIPINSTAT
  • DEVCFG
  • PWRSTATECTL
  • TINPSEL
  • TOUTPSEL
  • RSTMUXx
  • MAINPLLCTL0
  • DDR3PLLCTL0
  • PAPLLCTL0
  • PKTDMA_PRI_ALLOC


EDMAv3

What is Supported? What is not Supported?
  • TPCC and TPTC MMR and associated functionality

RAC2

What is supported? What is not supported?
  • RAC2 MMR and associated functionality


TAC 

What is supported? What is not supported?
  • TAC MMR and associated functionality


VCP2

What is supported? What is not Supported?
  • VCP2 MMR and associated functionality


TCP3D

What is supported? What is not supported?
  • TCP3d MMR and associated functionality
  • Error interrupt


TCP3E

What is supported? What is not supported?
  • TCP3e MMR and associated functionality
  • Error interrupt


FFTC

What is supported? What is not supported?
  • Supports IFFT and FFT
  • Sizes
  • 2a x 3b for 2 = a = 13, 0 = b = 1 – maximum 8192
  • 12 × 2a × 3b × 5c for sizes between 12 and 1296
  • 16 bits I/ 16 bits Q input and output
  • Dynamic and programmable scaling modes
  • Support for "FFT shift" (switch left/right halves)
  • Output data scaling
  • Ping/Pong input, output buffers
  • Support for cyclic prefix (addition and removal)


Multicore Navigator

What is supported? What is not supported?
  • Queue Manager
  • Packet DMA 
  • Timer
  • Accumulator PDSP
  • Interrupt Distributor 
  • Linking RAM
  • Queue Proxy
  • Multi-channel DMA


PCIe

What is supported? What is not supported?
* Register Only Model


UART

What is supported? What is not supported?
* Support to connect TCP/IP terminals like putty/TerraTerm/Hyperterminal


SRIO

  • What is supported?
  • What is not supported?
  • Logical and Transport layer SRIO
  • functionality is supported
  • SRIO Port 0
  • Message passing SRIO packets (Ftype = 11)
  • Type 9 SRIO packets
  • SRIO Tx and Rx is emulated thru reads and writes to TCP sockets
  • 8-bits and 16-bits device ID
  • Refer to TCI6616 Simulator SRIO model user guide for details.


  • Physical layer functionality
  • SERDES
  • SRIO Port 1, 2 and 3
  • SRIO packet formats other than Ftype = 11 (Direct IO, Retry logic, Maintenance packets, Doorbell operation, Cache coherence function) and Ftype = 9
  • Packet prioritization and reordering
  • Multicast device ID
  • Transmit and Receive teardown




Network Co-processor

  Packet Accelerator Sub-system
What is supported? What is not supported?
  • Independent Enhanced Packed Data Structure Processor cores (EPDSP)
  • 16-bit timers for use by the EPDSPs
  • Chunk Data Engines
  • 1st pass Lookup Table accelerators
  • 2nd pass lookup table accelerator
  • Basic Security Accelerator (NULL mode processing) with packet ingress/egress. This Security accelerator does not perform any encryption/decryption on packets, but passes it as-is.


  • Complete Cryptography Engine

Switch-Subsystem


What is supported?
What is not Supported?
  • 10/100/1000 Mbps modes (but not at speed)
  • Basic Address Lookup Engine
  • SERDES configuration
  • Rx and Tx Statistics update
  • Maximum frame size 9500 bytes
  • CRC32 generation and validation
  • Supports Layer 2 (Data Link Layer) messaging over the network
  • Ethernet packet transmission and reception
  • MDIO
  • Flow control
  • APO (Adaptive performance optimization)
  • Packet prioritization
  • Packet forwarding
  • ALE advanced features (Super, secure and block bits)


BCP

What is supported? What is not supported?
  • Bit co-processor functionality
  • Supports LTE, WiMAX, WCDMA (FDD), WCDMA (TDD) -- UL and DL


GPIO

What is supported? What is not supported?
  • GPIO MMR and associated functionality


Timer 64

What is Supported? What is not Supported?
  • Timer64 MMR and associated functionality


Interrupt Controller

What is supported? What is not Supported?
  • CP INTC functionality
  • One-to-one mapping of channels with host interrupts for all the INTC instances supported.





Limitations

Functional Simulator Limitations

  • Refer to "IP Model Details" for the list of IP model limitations
  • Refer to the simulator release notes for list of known/pending defects .

Cycle Approximate Simulator Limitations

  • The MMR of the following IP models are not supported in CX simulator
  • MSMC
  • XMC
  • EMIFv4
  • Debugger Limitation 
  • Debugger Reset is not supported 
  • User should quit the simulation and invoke it again
  • Loading Program (coff) from a core, into other core’s internal memory is not
    supported. In similar lines,
  • The viewing the contents of other core’s internal memory from a given core is not supported 
  • Mapping the CIO buffer’s into to other core’s internal memory and executing the application from a given core is not supported
  • When TCI6616/C6670/TCI6608/C6678/TCI6618 Device cycle-approximate simulator used in a CCS v5.0 environment, you may notice insufficient process memory error, while running large simulation. This is because of a process-memory limit enforced by the operating-system.
  • Refer to "IP Model Details" for the list of IP model limitations
  • Refer to the simulator release notes for list of known/pending defects .


Related Documents

  • Simulator Release notes
  • TCI6616/C6670/TCI6608/C6678 Device Simulator SRIO Model I/O user-guide
  • TCI6616/C6670/TCI6608/C6678 Device Simulator EMAC Model I/O user-guide
  • UART_Model_user_guide
  • Software Manifest Documents
  • TCI6616/C6670/TCI6608/C6678DeviceSims SW Manifest 2010
  • TCI6616/C6670/TCI6608/C6678DeviceSims SW Manifest 2010 (CCS direct)




Reporting Issues

Use the link below to file a defect/query on simulator

http://e2e.ti.com/support/development_tools/code_composer_studio/f/81.aspx

Update Releases

Version Date CCS5 stream  Windows Linux Release Notes Comments/readme
1.0.1.6 07/01/2011 CCS5.0.3

Patch over
CCS5.0.3 Download


Patch over
CCS5.0.3

Download

Support for register trace in CPU models. Readme for Sim CSP installation over CCS5.0.3
  •  The simulator CSP installer would ask for the CCS path to install the package.
  • User needs to select the path as <CCS v5 installation path>\ccs_base_5.0.x.xxxxx. For eg., D:\CCSv5_0_1_36\ccsv5\ccs_base_5.0.1.00036



02/07/2012 CCS5.1.1 Register trace feature is available in CCS5.1.1 base installation. No patch update required. Register trace feature is available in CCS5.1.1 base installation. No patch update required.