Please note as of Wednesday, August 15th, 2018 this wiki has been set to read only. If you are a TI Employee and require Edit ability please contact x0211426 from the company directory.

TI813x-DDR3-Init-U-Boot

From Texas Instruments Wiki
Jump to: navigation, search

TIBanner.png

TI813x-DDR3-Init-U-Boot


ReadMe First

The purpose of this document is to describe the approach to fine tune the DDR PHY on TI813x devices with SW leveling.SW leveling can be done in two methods

  • Byte wise SW leveling (For 32 bit DDR interface only)

Data macro for each byte lane is leveled independently. The Slave ratio search program will calculate optimal values for each byte lane.

  • Word wise SW leveling (For 32 bit or 16 bit DDR interface)

The Slave ratio search program will calculate common optimal value that works for all four byte lanes.

Recommendation: It is advised to perform byte wise leveling to compensate for the trace length delays for each byte lanes accurately, especially at higher frequencies of operation as compared to the word wise leveling.

This wiki page talks about Byte wise SW leveling.For word wise SW leveling follow the link http://processors.wiki.ti.com/index.php/TI813x-DDR3-Init-U-Boot_Wordwise_SWleveling

Prerequisites

  1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app File:TI813X Ratio Seed.zip
  2. CCS based program DDR3_SlaveRatio_ByteWiseSearch_TI813x.out File:DDR3 SlaveRatio ByteWiseSearch TI813x.zip
  3. TI813x U-Boot source code based on PSP release 04.04.00.01
  4. TI813X GEL File File:TI813x ddr3.zip
  5. U-Boot User Guide which is a part of the PSP release
  6. CCS 5.1 or above installed on Windows XP with Service Pack 2
  7. Details of CCS installation given in http://processors.wiki.ti.com/index.php/Category:Code_Composer_Studio_v5

Overview

In order to correctly setup DDR PHY in TI813x devices the approach used is Byte wise software leveling(To find the optimum DDR PHY slave ratio values for each byte lane).The DDR PHY has to be fine tuned based on the PCB trace lengths in order to compensate for the signal propagation delays accurately.

Important Note: SW leveling process is not intended to diagnose a non-working DDR interface. It is only intended for fine tuning the DDR PHY when the DDR interface is functionally working.

The leveling process involves the following steps

  1. Obtaining accurate PCB trace lengths (in inches) for the DDR CK trace and DQS trace (Data signal).
  2. Calculate the seed values to be input to the slave ratio search program ie:“DDR3_SlaveRatio_ByteWiseSearch_TI813x.out” as described in the subsequent sections.
  3. Configure the DDR controller (Also referred as EMIF) with the timing parameters calculated from the spreadsheet File:DM813x DDR Controller Register Configuration spreadsheet v1.0.zip based on the timing parameters mentioned in the data sheet of the specific DDR device being used.
  4. Configure the DDR PHY slave ratio registers with the respective seed values calculated from the spreadsheet.

Important Note: DDR memory access is expected to be working upon completion of the above mentioned steps. If not, choose a lower frequency of operation and repeat steps 1 to 4 until the basic memory access is working. It is meaningless to proceed further with SW leveling if the memory access is not working. Remaining steps will only help in getting the optimum DDR PHY slave ratio parameters.

5.Running the CCS based slave ratio search program on the device and collecting the optimum slave ratio values for the specific frequency of operation.

6.Programming the optimum values to the DDR PHY registers by replacing the seed values that were programmed initially.

7.To read back the programmed DDR controller and DDR PHY configurations,Load the gel file File:DM813x DDR Config ReadBack.zip and run the hot menu EMIF0_RegisterReadBack.


The slave ratio search program searches for the working range of the following Slave Ratio values based on the initial seed values keyed in on the command line,as explained in the next section.

  1. Read DQS Slave Ratio
  2. Read DQS Gate Slave Ratio
  3. Write DQS Slave Ratio
  4. Write DATA Slave Ratio

Please note that the DDR PHY has to be fine tuned each time when there is a change in the PCB layout(ie.when a new revision of the HW is made) or when the frequency of operation changes.

Obtaining the seed values

The seed values for the ratios may be obtained using the File:TI813X Ratio Seed.zip spreadsheet. The spreadsheet takes the following as inputs:

  1. DDR3 clock frequency
  2. CK and DQS trace lengths in inches for each of the byte lanes.

TI813x Excel screen.JPG


The user inputs should be entered on those cells that are marked green. Then spreadsheet will generate respective seed values at B17, B18 and B19 .These parameters should be passed to the CCS based slave ratio search program.

Running the CCS based slave ratio search program on the target hardware platform

Hardware and CCS Setup

NOTE

You can skip this step if CCS is already configured. Make sure the settings are as mentioned in the configure step.


  • Connect the JTAG emulator to the TI813x using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
  • Make sure the Boot Mode / Configuration Select Switch are set to all 0s.
  • Start CCSv5.1 by navigating to 'Start' menu in Windows XP
  • Select the workspace folder where you want to store your project
  • Use target configuration file ti813x.ccxml.Find the ccxml file attached for TI XDS560 PCI Emulator File:TI813X.zip
  • Download and copy ccxml file to the user workspace area,ie "CCSTargetConfigurations" folder of specific user.
  • Select View -> Target Configurations. Look for the target configuration TI813x.ccxml
  • Right click and click "Launch Selected Configuration" this should launch debug session
  • Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
  • In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
  • Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
  • Right click on the Cortex A8 core listed and click on "Connect Target"
  • A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Run menu and then click on Halt

Note: The steps mentioned above holds well for TI XDS560 Jtag emulator. User is advised to follow appropriate steps if a different emulator is being used

Generating the static values

Loading GEL File

  • Ensure that the GEL file File:TI813x ddr3.zip is copied to the Windows Machine
  • Select Tools -> GEL Files in CCS
  • This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
  • Navigate to the directory containing gel file and select TI813x_ddr3.gel
  • A "Scripts" menu item (on top) should now be available
  • Select Scripts -> Ti813x EVM DDR Configurations -> EVM_DDR3_EMIF0_400MHz_Config
  • This will perform DDR3 initialization.
  • On success, you should see following at the CCS console:
CortxA8: GEL Output: 	 ****  Configuring DDR PLL to 400 MHz......... 
CortxA8: GEL Output: 	 DDR ADPLLLJ CLKOUT  value is  = 400 
CortxA8: GEL Output: 	Ti813x DDR3 EVM EMIF0 configuration in progress......... 
CortxA8: GEL Output: 	Ti813x DDR,DMM PRCM configuration is Done 
CortxA8: GEL Output: 	Ti813x DDR PHY Configuration is Done 
CortxA8: GEL Output: 	Ti813x DDR IO Control Configuration is Done 
CortxA8: GEL Output: 	Ti813x VTP Configuration is Done 
CortxA8: GEL Output: 	Ti813x DMM LISA register Configuration is done 
CortxA8: GEL Output: 	Ti813x DDR3 EVM EMIF0 configuration is DONE.  
  

Note:Sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the Slave Ratio Search Program

  • At this point, A8 in in user(USR) mode (marked as USR in the bottom right corner of CCS Status Bar). It needs to be in Supervisor(SPV) mode to run U-Boot and the Linux Kernel. Follow these steps:
  1. Goto menu View -> Registers
  2. Expand CPSR
  3. Select “M” and set it to 0x13
  4. These steps set the CPSR.M to 0x13 (SPV mode).
  5. Goto Tools -> ARM Advanced Features select NEON Enabled
  • Select Run -> Load ->Load program. Select the CCS program DDR3_SlaveRatio_ByteWiseSearch_TI813x.out for loading.

Running the Slave Ratio Search Program

Run : 
DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0xFC 

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x34 

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x26 

Enter the input file Name 
Ti813x_EVM_SlaveRatio
*********************************************************
Byte level Slave Ratio Search Program Values
*********************************************************
                        BYTE3    BYTE2    BYTE1    BYTE0
*********************************************************
Read DQS MAX              6a       7b       6f       76
Read DQS MIN               9       12        7        d
Read DQS OPT              39       46       3b       41
*********************************************************
Read DQS GATE MAX        19d      1b8      1a5      188
Read DQS GATE MIN         58       36       1b        0
Read DQS GATE OPT         fa       f7       e0       c4
*********************************************************
Write DQS MAX             89       8d       7f       74
Write DQS MIN              0        0        0        0
Write DQS OPT             44       46       3f       3a
*********************************************************
Write DATA MAX            b1       b8       a9       b3
Write DATA MIN            42       44       41       4a
Write DATA OPT            79       7e       75       7e
*********************************************************
===== END OF TEST =====

Note : In the above example the output result gets saved in "Ti813x_EVM_SlaveRatio.txt" file.

Note:

  1. The slave ratio program expects EMIF0 to be configured for a base address of 0x8000:0000.Please note that user can choose a different base address for the DDR memory space (if needed) post the SW leveling.

The optimum slave ratio values may vary by small margin, if the SW leveling is performed multiple times. This is due to possible change in the environment variables such as Core/IO voltages and temperature.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot for the software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

  • Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h

The values obtained in the previous step need to be plugged under the TI813X appropriate #define in the order for each byte late suffixed with _BYTE<n>

/* TI813X DDR3 PHY CFG parameters   <emif0> */
#define DDR3_PHY_RD_DQS_CS0_BYTE0              0x41
#define DDR3_PHY_RD_DQS_CS0_BYTE1              0x38
#define DDR3_PHY_RD_DQS_CS0_BYTE2              0x46
#define DDR3_PHY_RD_DQS_CS0_BYTE3              0x37

#define DDR3_PHY_WR_DQS_CS0_BYTE0              0x39
#define DDR3_PHY_WR_DQS_CS0_BYTE1              0x3F
#define DDR3_PHY_WR_DQS_CS0_BYTE2              0x46
#define DDR3_PHY_WR_DQS_CS0_BYTE3              0x45

#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0         0xBD
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1         0xE0
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2         0x105
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3         0x12B

#define DDR3_PHY_WR_DATA_CS0_BYTE0             0x7C
#define DDR3_PHY_WR_DATA_CS0_BYTE1             0x73
#define DDR3_PHY_WR_DATA_CS0_BYTE2             0x78
#define DDR3_PHY_WR_DATA_CS0_BYTE3             0x6D

Note that the values used here are for representative purposes only. Use the values obtained from the CCS program over here

Register to U-Boot Macro Definition Mapping Table

Register Name Constant Name
File
SDRCR DDR3_EMIF_SDRAM_CONFIG ddr_defs_ti814x.h
SDRRCR DDR3_EMIF_REF_CTRL ddr_defs_ti814x.h
SDRRCR2 Not Used N/A
SDRTIM1 DDR3_EMIF_TIM1 ddr_defs_ti814x.h
SDRTIM2 DDR3_EMIF_TIM2 ddr_defs_ti814x.h
SDRTIM3 DDR3_EMIF_TIM3 ddr_defs_ti814x.h
PMCR Not Used N/A
PBBPR Not Used N/A
ZQCR DDR3_EMIF_SDRAM_ZQCR ddr_defs_ti814x.h
DDR_PHY_CR EMIF4_0_DDR_PHY_CTRL_1 ddr_defs_ti814x.h
PRI_COS_MAP Not Used N/A
CONNID_COS_1_MAP Not Used N/A
CONNID_COS_2_MAP Not Used N/A
RD_WR_EXEC_THRSH Not Used N/A
DDRIOCTRL DDR0_IO_CTRL ddr_defs_ti814x.h


  • Rebuild and flash U-Boot as described in the U-Boot user guide.