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TI813x-DDR3-Init-U-Boot Wordwise SWleveling

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TI813x-DDR3-Init-U-Boot


ReadMe First

The purpose of this document is to describe how to initialize DDR3 on TI813x using software leveling. This approach uses static values for the software leveling process.

Prerequisites

  1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app File:TI813X Ratio Seed.zip
  2. CCS based program DDR3_slave_ratio_search_TI813x.out File:DDR3 slave ratio search TI813x.zip
  3. TI813x U-Boot source code based on PSP release 04.04.00.01
  4. TI813X GEL File File:Ti813x ddr3.zip
  5. U-Boot User Guide which is a part of the PSP release
  6. CCS 5.1 or above installed on Windows XP with Service Pack 2
  7. Details of CCS installation given in http://processors.wiki.ti.com/index.php/Category:Code_Composer_Studio_v5

Overview

In order to correctly setup DDR3 in TI813x devices the approach used is software (slave ratio) leveling. The values to be used for software leveling are for specific board type and needs to be estimated using the CCS based program DDR3_slave_ratio_search_TI813x.out The program searches the window for the following Slave Ratio values on board based on the initial seed values to be keyed in on the command line(calculated based on DDR3 board topology), as explained in the next section.

  1. Read DQS Slave Ratio
  2. Read DQS Gate Slave Ratio
  3. Write DQS Slave Ratio

Note that this program needs to be run for each new board type and for each operating frequency of DDR3.

Obtaining the seed values

The seed values for the ratios may be obtained using the File:TI813X Ratio Seed.zip spreadsheet. The spreadsheet takes the following as inputs:

TI813x Excel screen.JPG

1. DDR3 clock frequency

2. CK and DQS trace lengths in inches for each of the byte lanes.


The user inputs should be on these cells that are marked green. Once these fields are input, feed the values for B17, B18 and B19 for respective parameters to the CCS program.

Hardware and CCS Setup

NOTE

You can skip this step if CCS is already configured. Make sure the settings are as mentioned in the configure step.


  • Connect the JTAG emulator to the TI813x using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
  • Make sure the Boot Mode / Configuration Select Switch are set to all 0s.
  • System Requirements – CCS 5.1 or above installed on Windows XP with Service Pack 2
  • Start CCSv5.1 by navigating to 'Start' menu in Windows XP
  • Select the workspace folder where you want to store your project
  • Use target configuration file ti813x.ccxml.Find the ccxml file attached for TI XDS560 PCI Emulator File:TI813X.zip
  • Download and copy ccxml file to the user workspace area,ie "CCSTargetConfigurations" folder of specific user.
  • Select View -> Target Configurations. Look for the target configuration TI813x.ccxml
  • Right click and click "Launch Selected Configuration" this should launch debug session
  • Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
  • In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
  • Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
  • Right click on the Cortex A8 core listed and click on "Connect Target"
  • A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Run menu and then click on Halt

Generating the static values

Loading GEL File

  • Ensure that the GEL file File:Ti813x ddr3.zip is copied to the Windows Machine
  • Select Tools -> GEL Files in CCS
  • This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
  • Navigate to the directory containing gel file and select Ti813x_ddr3.gel
  • A "Scripts" menu item (on top) should now be available
  • Select Scripts -> Ti813x EVM DDR Configurations -> EVM_DDR3_EMIF0_400MHz_Config
  • This will perform DDR3 initialization.
  • On success, you should see following at the CCS console:
CortxA8: GEL Output: 	 ****  Configuring DDR PLL to 400 MHz......... 
CortxA8: GEL Output: 	 DDR ADPLLLJ CLKOUT  value is  = 400 
CortxA8: GEL Output: 	Ti813x DDR3 EVM EMIF0 configuration in progress......... 
CortxA8: GEL Output: 	Ti813x DDR,DMM PRCM configuration is Done 
CortxA8: GEL Output: 	Ti813x DDR PHY Configuration is Done 
CortxA8: GEL Output: 	Ti813x DDR IO Control Configuration is Done 
CortxA8: GEL Output: 	Ti813x VTP Configuration is Done 
CortxA8: GEL Output: 	Ti813x DMM LISA register Configuration is done 
CortxA8: GEL Output: 	Ti813x DDR3 EVM EMIF0 configuration is DONE.  
  

Note:Sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the CCS app

  • At this point, A8 in in user(USR) mode (marked as USR in the bottom right corner of CCS Status Bar). It needs to be in Supervisor(SPV) mode to run U-Boot and the Linux Kernel. Follow these steps:
  1. Goto menu View -> Registers
  2. Expand CPSR
  3. Select “M” and set it to 0x13
  4. These steps set the CPSR.M to 0x13 (SPV mode).
  5. Goto Tools -> ARM Advanced Features select NEON Enabled
  • Select Run -> Load ->Load program. Select the CCS program DDR3_slave_ratio_search_TI813x.out for loading.

Running the app

Run : 
DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0xFC 

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x34 

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x26 

Enter the input file Name 
Ti813x_EVM_SlaveRatio 

********************************************************* 
The Slave Ratio Search Program Values are 
*********************************************************
PARAMETER		MAX	MIN	OPTIMUM	RANGE	
*********************************************************
Read DQS		70 	12 	41 	5e
Read DQS GATE		14e	56 	d2 	f8
Write DQS		72 	0 	39 	72
Write DATA		9f 	3e 	6e 	61
********************************************************* 
===== END OF TEST =====

In the above example the seed values are calculated based on the DDR3 board topology.

Based on the seed value, the search window may or may not converge for the slave ratios listed in Overview section.

Note : In the above example the output result gets saved in "Ti813x_EVM_SlaveRatio.txt" file.

You may choose to run it one more times to be sure that the converged "optimum values" are same. However, there can be small variations across different run based on the voltage and temperature on the board. In that case you can choose to enter converged values from any one of the run.

Note down the Optimum value for each slave ratio and enter either in the GEL file or the U-Boot code as described below.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot for the software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

  • Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h

The values obtained in the previous step need to be plugged under the TI813X appropriate #define in the order emif0

/* TI813X DDR3 PHY CFG parameters   <emif0> */
#define DDR3_PHY_RD_DQS_CS0_DEFINE              0x41
#define DDR3_PHY_WR_DQS_CS0_DEFINE              0x39
#define DDR3_PHY_RD_DQS_GATE_CS0_DEFINE         0xd2
#define DDR3_PHY_WR_DATA_CS0_DEFINE             0x6e

NoteNote: Please update the values in the following macros for PSP 04.04.00.01 Release. This will also affect the TI8148EVM configurations due to the common macro used.

/* TI814X DDR3 PHY CFG parameters   <emif0 : emif 1> */
#define DDR3_PHY_RD_DQS_CS0_DEFINE              ((emif == 0) ? 0x41 : 0x41)
#define DDR3_PHY_WR_DQS_CS0_DEFINE              ((emif == 0) ? 0x39 : 0x39)
#define DDR3_PHY_RD_DQS_GATE_CS0_DEFINE         ((emif == 0) ? 0xd2 : 0xd2)
#define DDR3_PHY_WR_DATA_CS0_DEFINE             ((emif == 0) ? 0x6e : 0x6e) 

Note that the values used here are for representative purposes only. Use the values obtained from the CCS program over here

Register to U-Boot Macro Definition Mapping Table

Register Name Constant Name
File
SDRCR DDR3_EMIF_SDRAM_CONFIG ddr_defs_ti814x.h
SDRRCR DDR3_EMIF_REF_CTRL ddr_defs_ti814x.h
SDRRCR2 Not Used N/A
SDRTIM1 DDR3_EMIF_TIM1 ddr_defs_ti814x.h
SDRTIM2 DDR3_EMIF_TIM2 ddr_defs_ti814x.h
SDRTIM3 DDR3_EMIF_TIM3 ddr_defs_ti814x.h
PMCR Not Used N/A
PBBPR Not Used N/A
ZQCR DDR3_EMIF_SDRAM_ZQCR ddr_defs_ti814x.h
DDR_PHY_CR EMIF4_0_DDR_PHY_CTRL_1 ddr_defs_ti814x.h
PRI_COS_MAP Not Used N/A
CONNID_COS_1_MAP Not Used N/A
CONNID_COS_2_MAP Not Used N/A
RD_WR_EXEC_THRSH Not Used N/A
DDRIOCTRL DDR0_IO_CTRL ddr_defs_ti814x.h


  • Rebuild and flash U-Boot as described in the U-Boot user guide.