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TMS320C5504/05/14/15/32/33/34/35 Power Consumption Summary
- 1 Overview
- 2 Activity-Based Models
- 3 Using the Power Estimation Spreadsheet
- 4 Using the Results
- 5 Example
- 6 Limitations
- 7 Download
- 8 Related
- 9 C55xx Comparison
- 10 References
This article assists in estimating the power consumption for the TMS320C5504/C5505/C5514/C5515 and TMS320C5532/C5533/C5534/C5535 digital signal processors (DSPs). Power consumption on these devices is highly application-dependent, so a spreadsheet is provided to estimate power consumption. The spreadsheet allows you to enter parameters that closely resemble the application and generate a realistic estimate of DSP power consumption based on your input. It also allows designers the ability to test the efficiency of different configurations before they assemble any hardware or write any code.
To obtain good results from the spreadsheet, realistic usage parameters must be entered. The low-core voltage and other power design optimizations allow these devices to operate with industry-leading performance, while maintaining a low power-to-performance ratio.
The data presented in the accompanying spreadsheet was measured from nominal units. Although this spreadsheet was developed for the C5515, it can be used to model power consumption on the C5504, C5505, C5514, C5532, C5533, C5534, and C5535 devices. Features not supported on these devices should not be enabled in the spreadsheet.
The spreadsheet discussed in this application report can be downloaded from the URL listed in the Download Section.
|CVDD (V)||ANA (V)||PLL(V)||DVDDIO (V)||EMIF (V)||USB3.3 (V)||USB1.3 (V)||DRTC (V)||CRTC (V)||LDOI (V)||Configuration||CPU Frequency (MHz)||Total Power (mW)|
|0||0||0||0||0||0||0||3.3||1.3||1.8||RTC power only||0|| 0.2|
|1.05||1.3||1.3||1.8||0||0||0||3.3||1.05||1.8|| Standby Power
|1.05||1.3||1.3||1.8||0||0||0||3.3||1.05||1.8|| Voice Encoder
|1.05||1.3||1.3||3.3||0||0||0||3.3||1.05||3.3|| Typical - 60MHz
|1.3||1.3||1.3||3.3||3.3||0||0||3.3||1.3||3.3||Typical - 100MHz||100||51.9|
|1.4||1.3||1.4||3.3||3.3||3.3||1.3||3.3||1.3||3.3||Typical - 150MHz||150||149.9|
Power consumption is application-dependent on the TMS320C5504/C5505/C5514/C5515 and C5532/C5533/C5534/C5535 devices. This means the power consumption for a particular application depends on the level of CPU and peripheral activity models. You must have a clear understanding of the CPU, peripherals, and I/O activity levels of the application to get a realistic result. The output of the power estimation spreadsheet can aid in power supply design or battery life prediction. The model used in this spreadsheet is based on two modes of power consumption: static and active power. With this approach, each of the DSP components (CPU, peripherals, and I/O pins) can be isolated to determine how it contributes to the overall power consumption.
Static power is what is consumed when the on-chip oscillator is shut down (the clock generation domain is idle). If an external clock source is used instead of the on-chip oscillator, the static power is consumed when the external clock source is stopped; therefore, no activity on the DSP is being clocked. The static power consumption depends purely on the core, I/O voltages and the device operating temperature.
Active power is what is consumed by the active parts of the DSP. These include the CPU, peripherals,and I/O pins associated with the peripherals. The active power consumption is based on the supply voltages, operating frequency, and how each peripheral is configured. To get a better understanding of the distribution of the active power consumption, each module can be evaluated independently.
The parameters used to describe each module activity are:
- Frequency is the operating frequency of a module or it is the operating frequency of the interface to that module.
- Idle Status indicates whether the module is in idle or in active state.
- %Utilization is the percentage of activity in a module relative to its maximum.
However, each module may not include all of these parameters.
Each of the following modules and sub-modules can be configured by the user in the power estimation spreadsheet, within realistic operating parameters.
- Phase-Locked Loop (PLL)
- Central Processing Unit (CPU) and CLKOUT
- External Memory Interface (EMIF)
- Liquid Crystal Display Controller (LCDC)
- Direct Memory Access (DMA) (Up to 4 channels)
- Inter-IC Sound (I2S) (Up to 4 channels)
- MultiMedia Card/Secure Digital (MMC/SD) (Up to 2 channels)
- Serial Port Interface (SPI)
- Universal Asynchronous Receiver/Transmitter (UART)
- Inter-Integrated Circuit (I2C)
- General-Purpose Timer (Up to 3 timers)
- Real-Time Clock (RTC) and RTC CLKOUT
- General-Purpose Input/External Flag Output (GPIO/XF)
- Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
Using the Power Estimation Spreadsheet
The power estimation spreadsheet involves entering the appropriate usage parameters as input data in the spreadsheet. Cells that are designed for user input are white in color. The following steps explain how to use the spreasheet:
- Select the voltage,PLLs configuration and device frequency for the estimated end application.
- Fill in the appropriate module use parameters
The spreadsheet takes the provided information and displays the details of power consumption for the chosen configuration.
As the spreadsheet is being configured, not all settings are checked for conflicts, e.g. peripheral clock frequency out of allowed range, etc. Consult the device-specific data manual for max frequency limitations. For best results, enter the information from left to right starting at the top and moving downward.
Although the spreadsheet was developed for the C5515 device, it can be used to model power consumption on the C5504, C5505, C5514, C5532, C5533, C5534, and C5535 devices. Features not supported on these devices should not be enabled in the spreadsheet.
Choosing Appropriate Values
The accuracy of the results produced by the power estimation spreadsheet depends on how closely the parameters entered match with those of the actual system. Each module must be considered separately for a given process and you must account for all activity included in a given operation. For instance, EMIF activity is not included in the CPU activity when the code is being executed from external memory. The EMIF activity must be included separately in the EMIF section of the spreadsheet.
In some cases the frequency parameter for a particular module denotes the output frequency of that module. For others, it denotes the internal operating frequency of the module.
The PLL frequency is simply the output frequency of the clock generator in the PLL-lock mode. The PLL synthesized is distributed to the CPU and the peripheral. Some of the peripheral's internal logic runs at the same rate as the CPU. Other peripherals support a user-configurable prescaler to run the module at an integer fraction of the CPU clock. For example, the DMA's internal logic runs at the same rate as the CPU, but the I2C or the MMC/SD modules can be programmed to run its internal logic (state machine) at a much slower speed. The clock frequency of the PLL and module clocks should not be set in a manner that violates the frequency restrictions imposed by the device data sheet and module reference guide. The PLL operation frequency ranges between 60 and 150 MHz. Note: It requires an external clock to support over 120MHz.
- CPU and CLKOUT
The clock frequency of the CPU can be set to the same frequency of the PLL output or divided clock frequency. The CLKOUT frequency is programmable and should be set as in range specified by the spec. The CPU operation range is 0–50/60/75 MHz at 1.05-V CVDD and 0–100/120 MHz at 1.3-V CVDD. The CPU operation range is 120-150 MHz at 1.4-V CVDD.
The frequency field represents the EMIF CLKMEM frequency. External clocking of the EMIF is not supported. EMIF operation frequency is 0–100 MHz if the CPU is under 100 MHz. If the CPU is over 100 MHz, then EMIF should run at half of the CPU frequency.
The frequency field for LCDC indicates the frequency of transmit data rate. The operation range is 0–12 MHz.
The internal operating frequency of the DMA is automatically set to the CPU clock and is not user-configurable.
The frequency field for I2S indicates the frequency of transmit or receive clocks (BCLK).
The frequency field of the MMC/SD interface operates in a range between 0 and 50 MHz, or half of the CPU frequency.
This frequency field indicates the frequency of SPI clock. The operation maximum frequency is 30 MHz, or one-quarter of the CPU frequency.
The frequency field for the UART interface clock accepts only values between 0 and up to one-sixteenth of the CPU frequency.
The frequency field for the I2C interface clock accepts only values between 100 kHz and 400 kHz.
The frequency, in this case, indicates the output frequency or the periodic frequency. The timer output frequency depends on the timer prescaler and the period register values. In the spreadsheet, none of the usage parameters are configurable on the Watchdog Timer (WDT) module. The current consumed by only the WDT while active and running is extremely small; therefore, its contribution to the total current consumed by the device is assumed to be negligible.
The universal serial bus (USB) internal clock is set to 12 MHz and cannot be configured on the spreadsheet.
- RTC and RTC CLKOUT
The default RTC frequency is 32.768 kHz and is not user-configurable. In addition, none of the usage parameters in the spreadsheet are configurable on the RTC module. The RTC CLKOUT frequency is 32.768 kHz.
The frequency input for GPIO and XF indicate the frequency at which the states of the GPIO pins are updated. The maximum output frequency of GPIO is 1/6 CPU frequency.
- SAR ADC
The current version of the spreadsheet estimates SAR current consumption with SAR programmed for the maximum sampling rate of 2 MHz. To minimize the power consumption of the ADC state machine, the SAR clock should be programmed to the lowest possible frequency.
Utilization is explicitly defined for each module to provide a more accurate estimate of power consumption. If a module is not listed, then it is assumed to be in use whenever it is not idle, or, in some cases, like RTC and WDT, the contribution of the modules, while active and being maximally utilized, is small enough to be neglected as compared to the total current consumed.
Since the CPU can be involved in a wide range of activities, it is difficult to provide an exact CPU utilization number. Whenever the CPU is active (non-idle), it is executing some type of instruction. For this reason, 0% activity is assumed as a CPU executing the smallest amount of power the CPU can consume while active. Conversely, 100% activity is assumed as the most power-intensive instruction—the dual multiply and accumulate. All other instructions fall somewhere in between. No single algorithm will achieve 100% utilization, but some highly optimized functions can come close. On the other hand, when the CPU performs control-oriented tasks, it consumes far less current. Assume, for example, that a certain application executes control code half of the time and a highly optimized algorithm for the other half. If the control code is estimated to be at 30% utilization, and the dense DSP code is estimated to be at 90% utilization, the overall utilization will be 60% (30% x 50% + 90% x 50%). If the application spent more time executing the optimized algorithm, utilization would obviously go up, and vice versa. Examining individual segments of an application and estimating the time spent and the CPU utilization in each segment can provide a more accurate percentage of the CPU utilization.
EMIF utilization is related to the maximum bandwidth of the EMIF. One hundred percent utilization corresponds to the maximum transfer rate for a given frequency when doing these types of transfers. This number will be scaled down by both slower and less frequent transfers. In case of SDRAM, for writes, 100% utilization or maximum throughput is one 16-bit word/cycle (with write posting enabled). (EMIF is configured to communicate with the SDRAM using the divide-by-1 clock mode, i.e., CLKMEM equals the CPU clock frequency.) The utilization percentage is defined as the throughput of the application under question, divided by the maximum throughput rates as defined above. For example, CPU reading data from SDRAM at the rate of a 16-bit word every 20 cycles yields 20% EMIF utilization.
LCDC utilization is defined as the percentage of time that the LCDC is transferring data. The rest of the time the LCDC is assumed to be not transferring any data.
DMA utilization for a given channel is based on the maximum attainable data transfer rate between the SARAM and DARAM port, which is one 32-bit transfer per CPU cycle. Twenty-percent DMA channel utilization would yield one 32-bit transfer per five CPU cycles.
I2S utilization is defined as the percentage of time that the I2S is transferring data. The rest of the time the I2S is assumed to be not transferring any data.
MMCSD utilization is defined as the percentage of time that the MMCSD is transferring data. The rest of the time the MMCSD is assumed to be not transferring any data.
SPI utilization is defined as the percentage of time that the SPI is transferring data. The rest of the time the SPI is assumed to be not transferring any data.
UART utilization is defined as the percentage of time that the UART is transferring data. The rest of the time the UART is assumed to be not transferring any data.
I2C utilization is defined as the percentage of time that the I2C is transferring data. The rest of the time the I2C is assumed to be not transferring any data.
Timer utilization is defined as the percentage of time that the timer is counting.
USB utilization is based on the maximum attainable data transfer rate between the DSP memory and the USB host device.
Utilization for general-purpose outputs is the percentage of time that they are switching at their specified frequency.
- SAR ADC
SAR utilization is defined as the percentage of time that the SAR is performing the analog-to-digital conversion.
Some modules, outlined in the following sections, have additional parameters for a more granular estimation of the power consumption.
This value lists the total number of MMC/SD instances that are consuming active power.
This value lists the total number of Timer instances that are consuming active power.
This value lists the total number of GPIO pins that are consuming active power.
The results are estimated in the spreadsheet and displayed in milliamps (mA) or milliwatts (mW). Click the units in the total row of the calculated results and use the drop-down menu to select the desired units.
Peripheral enabling, disabling and shut off
As mentioned previously, the C5515 device provides the capability to disable modules that are not being used via the clock gating. When a peripheral is disabled, its clock is turned off reducing the power consumption of the device.
The spreadsheet accommodates this power saving feature by including fields from which a peripheral can be specified as disable or enabled.
If a module is not used for a given application, then it is recommended to keep it in a disabled state.
It is possible that the module is kept enabled but has no activity. To achieved this, program the % utilization and/or the frequency fields to a value of 0, then the numbers in the module's row will be indicative of the power consumed by clocking the module.
A peripheral can be shut off if the peripheral is never used in the design or not supported.
Using the Results
The results presented in the spreadsheet are based on measured data using the C5515 device. Most production units, if correctly used, will typically consume power that is around the value given in the spreadsheet. Transient currents can cause power to spike above the estimated value for short periods, but long-term power consumption should be similar to the spreadsheet value. This allows for better estimates of power supply requirements and more accurate battery life predictions.
Note: Before using the spreadsheet, open it and verify that you have enabled the macro.
The following examples demonstrate how to choose appropriate values for a particular application. These values may be imported into the spreadsheet by clicking the appropriate macro button.
The RTC Only macro button reports the power consumed with 1.3 volts applied to RTC CVDD, 3.3V volts to DVDDRTC and 1.8V to LDOI. Other rails are powered off.
The Standby (IDLE3) macro button reports the power consumed with the RTCCLOCK. PLL is powered down/disabled and the system is operating in PLL bypass mode with the RTCCLOCK as the system clock. CPU is in IDLE state which it's in active. All peripherals are disabled except EMIF and USB are shut off.
The Voice Encoder macro button reports the power consumed on voice encoder example running. PLL sets to 80 MHz and CPU runs at 40 MHz. One DMA controller is on and patches audio sample data from one active I2S port. CPU is utilized about 88% doing voice encoding. Audio sampling rate is 16 KHz.
The Typical-60 MHz macro button can be used to quickly visualize the use case scenario. The details of the peripherals and their operating conditions used in this scenario are for voice encoder:
- Core Voltage: 1.05V
- ANA Voltage: 1.3V
- PLL Voltage: 1.3V
- DVDDIO Voltage: 3.3V
- LDOI Voltage: 3.3V
- PLL input clock: 32.768 KHz
- CPU Frequency: 60 MHz
- CPU: Enabled, 70% Utilization
- I2S: Enabled and running at 1.5 MHz, 100% Utilization
- DMA: Enabled and 2% Utilizaion
- UART: Enabled and running at 3 MHz, 50% Utilization
- I2C: Enabled, 400KHz, 10% Utilization
All other modules are not used and disabled. EMIF and USB are shut off.
The Typical-100 MHz macro button is the same as the Typical-100 MHz macro button, except that core voltage is at 1.3 volts, EMIF enabled and the device is running at 100 MHz.
The Typical-150 MHz macro button is the same as the Typical-150 MHz macro button, except that core and PLL voltage are at 1.4 volts, USB enabled and the device is running at 150 MHz.
The current implementation of the power estimation spreadsheet has the following limitations:
- All measurements have been performed with a 32.768Khz RTCCLK provided by an RTC oscillator under CPU 120 MHz. Over 120 MHz for CPU frequency the external 12 MHz oscillator is used for PLL input.
- All measurements are done at a room temperature.
|A||January 2012||Initial Release|
|B||March 2013||Including 150 MHz device, DMA and I2S sub modules can be independently selected, more example Macros added|
Below table illustrates the comparison of C55xx devices.
|C55xx Devices||Package||Max Frequency of Part||Max Frequency of Part||Max Frequency of Part||Peripherals Differences||Internal Memory Size||EMIF - Max Memory Size||Co-processor||LDOs|
|Core Voltage 1.05V||Core Voltage 1.3V||Core Voltage 1.4V|
|C5504A10||196 ZCH (10x10 mm BGA)||60MHz||100MHz||N/A||USB||256KB||8MB||N/A||ANA_LDO|
|C5504A12||196 ZCH (10x10 mm BGA)||75MHz||120MHz||N/A||USB||256KB||8MB||N/A||ANA_LDO|
|C5504A15||196 ZCH (10x10 mm BGA)||75MHz||120MHz||150MHz||USB||256KB||8MB||N/A||ANA_LDO|
|C5505A10||196 ZCH (10x10 mm BGA)||60MHz||100MHz||N/A||USB, LCD, SAR & ADC||320KB||8MB||FFT||ANA_LDO|
|C5505A12||196 ZCH (10x10 mm BGA)||75MHz||120MHz||N/A||USB, LCD, SAR & ADC||320KB||8MB||FFT||ANA_LDO|
|C5505A15||196 ZCH (10x10 mm BGA)||75MHz||120MHz||150MHz||USB, LCD, SAR & ADC||320KB||8MB||FFT||ANA_LDO|
|C5514A10||196 ZCH (10x10 mm BGA)||60MHz||100MHz||N/A||USB||256KB||8MB||N/A||ANA_LDO, USB_LDO & DSP_LDO|
|C5514A12||196 ZCH (10x10 mm BGA)||75MHz||120MHz||N/A||USB||256KB||8MB||N/A||ANA_LDO, USB_LDO & DSP_LDO|
|C5515A10||196 ZCH (10x10 mm BGA)||60MHz||100MHz||N/A||USB, LCD, SAR & ADC||320KB||8MB||FFT||ANA_LDO, USB_LDO & DSP_LDO|
|C5515A12||196 ZCH (10x10 mm BGA)||75MHz||120MHz||N/A||USB, LCD, SAR & ADC||320KB||8MB||FFT||ANA_LDO, USB_LDO & DSP_LDO|
|C5532A05||144 ZHH (12x12 mm BGA)||50MHz||N/A||N/A||N/A||64KB||N/A||N/A||ANA_LDO|
|C5532A10||144 ZHH (12x12 mm BGA)||50MHz||100MHz||N/A||N/A||64KB||N/A||N/A||ANA_LDO|
|C5533A05||144 ZHH (12x12 mm BGA)||50MHz||N/A||N/A||USB||128KB||N/A||N/A||ANA_LDO & USB_LDO|
|C5533A10||144 ZHH (12x12 mm BGA)||50MHz||100MHz||N/A||USB||128KB||N/A||N/A||ANA_LDO & USB_LDO|
|C5534A05||144 ZHH (12x12 mm BGA)||50MHz||N/A||N/A||USB||256KB||N/A||N/A||ANA_LDO, USB_LDO & DSP_LDO|
|C5534A10||144 ZHH (12x12 mm BGA)||50MHz||100MHz||N/A||USB||256KB||N/A||N/A||ANA_LDO, USB_LDO & DSP_LDO|
|C5535A05||144 ZHH (12x12 mm BGA)||50MHz||N/A||N/A||USB, LCD, SAR & ADC||320KB||N/A||FFT||ANA_LDO, USB_LDO & DSP_LDO|
|C5535A10||144 ZHH (12x12 mm BGA)||50MHz||100MHz||N/A||USB, LCD, SAR & ADC||320KB||N/A||FFT||ANA_LDO, USB_LDO & DSP_LDO|