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TMS320C6000 DSP Optimization Workshop

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The C6000 Optimization Workshop focuses on writing high performance code for the TMS320C6000 DSP. By examining the CPU architecture, TI DSP Development Tools, and other system issues you should leave the class with a good understanding of the techniques involved in writing good C6000 code. While high performance coding is the primary concern, the workshop also addresses other important system optimization topics: minimizing code size; numerical issues with fixed-point processors; writing interruptible, high-speed code; cache memory and packaging xDAIS and iUniversal algorithms.

By thoroughly investigating fundamental aspects of the TMS320C6000 VelociTI architecture, combined with coding techniques such as software pipelining, you will have a solid understanding of how this multiple issue processor obtains its high performance. In addition you will have the knowledge necessary to make trade-offs between processor performance and system memory requirements.

This workshop covers the architecture of all C6000 devices including C62x, C67x/C672x, C64x/C64x+, C674x, and C66x.

Attend a Live Workshop

You can find the workshop schedule and enrollment information for a live TMS320C6000 DSP Optimization Workshop here: TMS320C6000+ DSP Optimization Workshop

Workshop Version

C6000 Optimization Workshop (OP6000)
Released: March 2011
Version: 1.51

Revision Note:

Lab guide v1.51a released May/06/2011. No course content changes, but fixed error in how lab exercises PDF was compiled. (Also created a "for printing" version that removes 2 large optional labs - this should reduce printing costs - and wasted paper. If students want to do these in-class, they can use the PDF file found in the lab folder.)

Workshop Materials