Introduction

Many of the C2000 devices have internal circuitry to detect if a watchdog reset (WDRST) or a POR/external XRS has occurred. This article describes how this circuitry works and the system requirements on XRS if the WDFLAG is to be used in a system.

WDFLAG Behavior

The WDFLAG bit in the Watchdog module is meant to allow a system to distinguish between a POR/external XRS and a watchdog reset (WDRST). There is circuitry within the device that samples the XRS line, after a delay, to distinguish between a watchdog reset (WDRST) and a normal reset.

When the XRS line is pulled low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if the XRS signal is sampled high after a delay of 8192 * 4 + 512 OSCLK cycles. If the XRS signal is sampled low at this time, then the WDFLAG bit will remain at 0. Therefore to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then this sampling time.

Note: OSCCLK is four times SYSCLKOUT at reset. This is where the multiply-by 4 comes from in the delay formula. WDRST is 512 OSCCLKS so the delay is added on to this value.

The following summarizes how the WDFLAG bit behaves for each type of reset:

On Power-up

In this case, the desire is for WDFLAG == 0 to indicate the reset was not caused by a WDRST. To achieve this, XRS must be be held low for at least (8192 * 4 + 512) OSCCLK cycles. At this point, the XRS line will be sampled and if it is low, the WDFLAG will remain at 0. For Piccolo, the time is ~3.7ms for a 9MHz OSCCLK.

If the XRS pin is not still low at the sampling time, then the WDFLAG will be set, incorrectly indicating that the watchdog fired the reset.

Note: A lower-bound value of 9 MHz, instead of 10 MHz, has been used for the OSCCLK frequency. This is to account for oscillator frequency deviation before calibration.

Note: The pulse width for the internally generated POR signal in Piccolo is about ~800 uS. Since the sampling concept is applicable for POR also, then in this case the WDFLAG bit will always be 1 on a internally generated BOR/POR

On reset initiated by XRS (long after power-up)

The desire in this case is for WDFLAG == 0. To achieve this, once again, XRS must be held low for at least (8192 * 4 + 512) OSCCLK cycles. This is ~3.7ms for a 9 MHz OSCCLK.

On a Watchdog initiated reset (WDRST)

In this case we want the WDFLAG == 1. In this case the XRS signal is floating. The WDRST will pull the XRS line low for just 512 OSCCLK cycles. When the WDRST releases the line, it will return to a high state. The WDFLAG is set only after (8192 * 4) OSCLK cycles from the time when the WDRST is de-asserted (goes high). Since WDRST is 512 oscclk cycles so the flag will be set ~3.7 ms after the start of WDRST (when it goes low).

Watchdog WDRST and XRSn on a Watchdog Reset (3.3-3.7ms for 10-9MHz OSCCLK)

Connections for XRS pin

Depending on application needs, the XRS pin may have to be treated differently across designs.

Case 1) Differentiation between WDRST and POR/external reset is not required

If differentiating between a watchdog reset and a POR/external reset is not a concern, then a pull-up resistor on the XRS pin (for noise immunity reasons) would suffice. The controlCARD has a simple pull-up and falls into this case. The below figure shows why using a simple RC circuit can result in the WDFLAG being incorrectly set if OSCCLK = 9 MHz.

RC reset circuit incorrectly sets the WDFLAG

Case 2) Differentiation between WDRST and POR/XRS is required

If differentiating between a Watchdog Reset and a POR/external reset is needed, additional design considerations are warranted.

There is a circuit in the device that delays the sampling of the XRS line to distinguish between a watchdog reset (WDRST) and a normal reset. To distinguish between a watchdog reset and an external device reset, the external reset must be longer in duration than the watchdog pulse (512 OSCCLK cycles) + a 8192 SYSCLKOUT cycle delay.

On reset, SYSCLKOUT = OSCCLK/4. Therefore, the external reset pulse needs to be longer than 3.7 ms [(512 + 8192*4)/9 MHz].

Note: A lower-bound value of 9 MHz has been used for the OSCCLK frequency. This is to account for oscillator frequency deviation before calibration.

A R-C circuit may be employed as shown. In this case, current calculations on the diode should be done assuming the cap is fully charged at 3.3V. If the diode cannot handle the discharge current, then a current limiting resistor in series with the diode may be needed.

Reset Circuit to Detect WDRST vs POR/external Reset

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