AIF SW Library

=Components=

The AIF software library is designed for IQ data transfers between downlink/uplink embedded processors and a high speed serial interface in a transmission chain in CPRI mode. It has been designed and developed by Texas Instruments and hence provides users with the most advanced optimization techniques on the TMS320C6416™ DSP platform.

This AIF software library is composed of:


 * Enhanced Direct Memory Access EDMA3 Controller, for data transfers between the external memory of the TMS320C6474 and the outbound/inbound AIF RAM, associated with edma_setup.c
 * Frame synchronization module FSYNC, used to mark the boundaries of UMTS frames and system time in order to generate events synchronized with this time, associated with fsync_setup.c
 * Antenna Interface module AIF, for downlink/uplink data transfers, associated with aif_setup.c
 * The AIF module interoperability test, consists of a transmission chain in CPRI protocol


 * 1) First visit the EDMA3 page to familiarize yourself with how the EDMA3 functions and to see how to initialized the EDMA3.'''
 * 2) Upon hardware setup completion, there are four EDMA3 transfers need to be configured:
 * Outbound data transfer from the Tx processor to the outbound AIF RAM every 4 chips
 * Outbound control words transfer from the Tx processor to the outbound AIF RAM every 32 chips
 * Inbound data transfer from the inbound AIF RAM to the Rx processor every 8 chips
 * Inbound control words transfer from the inbound AIF RAM to the Rx processor every 32 chips

Outbound data transfer from the Tx processor to the outbound AIF RAM every 4 chips The DMA switch fabric is configured to receive a tick every 4 chips. Upon reception of these ticks, PaRAM set is configured for outbound data transfer from the external memory of the Tx processor (agDlCircBuff) to the AIF RAM (outbound data flow).

Outbound control words transfer from the Tx processor to the outbound AIF RAM every 32 chips

Every 32 chips, the DMA switch fabric receives a counter-based trigger event. During this tick, the EDMA3 accomplishes outbound control word transfers from the external memory of the Tx processor (agDlCwCircBuff) to the outbound AIF RAM.

Inbound data transfers from the inbound AIF RAM to the Rx processor every 8 chips

The reception of a tick for every 8 chips allows PaRAM set configuration. This setup is necessary for inbound data transfers from the AIF RAM to the external memory of the Rx processor (inbound data flow). This configuration allows an EDMA configuration to read 8 chips of data from all AxC, which are stored in the inbound AIF RAM. These data are transferred to the external memory of Rx processor (agUlCircBuff) owing to the EDMA3 controller. The AIF inbound RAM can store a maximum of 32 chips for each oversampled antenna stream. The memory arrangement for storing inbound antenna streams Rx processor in shown in the figure below:

Figure 9: Memory arrangement for storing inbound AxCs

Note that an interrupt upon transfer completion is activated for the inbound data transfer. The presence of this interrupt is to be updated of the quantity of data transferred to the external memory of the Rx processor since the antenna interface is static in nature; it continuously receives antenna data.

Inbound control words transfers from the inbound AIF RAM to the Rx processor every 32 chips

Similar to the outbound control word transfers, every 32 chips, the DMA switch fabric receives a counter-based trigger event. Upon reception, the EDMA3 accomplishes inbound control word transfers from the inbound AIF RAM to the external memory of the Rx processor (agUlCwCircBuff).

Closing EDMA3 module,
For more info, See Article : AIF