AIF Data Flow

AIF Data Flow
An AIF module in operation is static in nature. It receives and transmits IQ data continuously; it acts as a buffer to make sure that the system will not lose any samples. This section explains the AIF data flow for outbound/inbound data transfers. The transition from a state to another state machine is handled on the hardware part. However, user may also force the state machine in the software part (by writing to the bits TM_FORCE_TX_STATE and RX_FORCE_RX_STATE in the Tx MAC and Rx MAC Configuration Registers).
 * 1) DL Data Flow – From Tx processor to outbound AIF RAM

Transmitter Synchronization State Machine

With CPRI mode, there are three states in the transmitter state machine: OFF, IDLE, and FRAME_TX.

Outbound data transmission (Tx processor --> outbound AIF RAM)

Initially, outbound data are written in a data buffer, agDlCircBuff situated in the external memory of the embedded processor. The EDMA3 triggers occur once every four chips. Four chips of outbound data are transfer for all antenna streams per link into the outbound AIF RAM. The EDMA starts transferring data from the Tx embedded processor by the location specified by the read location stored in the active EDMA PaRAM entry and it increments the read location by four chips. The antenna interface runs a transmit frame synchronization protocol, in accordance to the transmit synchronization state machine. Once the Tx link is in the FRAME_TX state, it grabs data from the AIF RAM and encodes as necessary so that a CPRI complaint stream is produced at the SERDES output. Any synchronization required to put the Tx MAC in the FRAME_TX state must happen before the downlink is set up.

 


 * 1) EDMA3 data transfer from Tx processor
 * 2) Data buffer RAM stores organized data received from the Tx processor
 * 3) Message construction to be sent to AxCs, it also include K28.5 characters
 * 4) Interleaves the alternating IQ bits  ó from I0I1..I15Q0Q1..Q15  to CPRI data format (I0Q0I1Q1….I15Q15)
 * 5) Tx MAC performs the 8b/10b encoding. It also creates the frame structure based on the programmed link rate. Data are moved from the VBUS_CLK domain to the BYTE_CLK domain.
 * 6) There are 2 SERDES macros; 1 has 4 links and the other has 2 links. Each macro has a SERDES reference clock in a 12-byte clock domain. These 6 links can be configured to run on 1x, 2x or 4x line rates (software setup in vConfigAif). The encoded 10 bit data are converted into serial data stream and transmitted with LSB first.
 * 7) User plane data exits the AIF module as serial DL data.


 * 1) UL Data Flow – From inbound AIF RAM to Rx processor 

Receiver Synchronization State Machine

In CPRI mode, there are four states in the receiver state machine: XACQ1, XACQn, XSYNCn and HFSYNC.



Inbound data transmission (inbound AIF RAM --> Rx processor) The frame synchronization provides an eight-chip tick per link to the EDMA3. Upon receiving this tick, the EDMA transfers eight chips worth of data for all active antenna streams for the link from AIF RAM to the external memory in the UL embedded processor. The PaRAM entries ensure that the antenna streams are being transferred in the correct buffer, agUlCircBuff.




 * 1) User plane data enter the AIF module as serial UL data.
 * 2) There are 2 SERDES macros; 1 has 4 links and the other has 2 links. Each macro has a SERDES reference clock in a 12-byte clock domain. These 6 links can be configured to run on 1x, 2x or 4x line rates (software setup in vConfigAif). The serial UL data entered in the Rx SERDES block are converted into 10 bit clocks.
 * 3) Rx MAC performs the 8b/10b decoding. Once decoded, the data are in the form of CPRI basic frame structure for 1 chip. Data are also moved from the BYTE_CLK domain to the VBUS_CLK domain. (the data format observed are done by hardware, developer only need to activate the Rx MAC as well as to configure the pi offset, lost of detect threshold, maximum master frame offset and valid master frame offset values).
 * 4) De-interleaves the alternating IQ bits  ó from CPRI data format (I0Q0I1Q1….I7Q7) to I0I1..I7Q0Q1..Q7.
 * 5) Protocol decoder extracts AxC messages, organized the data before sending to the data buffer RAM.
 * 6) Data buffer RAM stores organized data received from the protocol decoder. (refer to slide number 3 for an example of data format in data buffer RAM)
 * 7) EDMA3 data transfer to the external memory of the Rx processor