AM57x PRU Read Latencies

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= Introduction =

The AM57x PRU-ICSS is a master initiator with access to all SoC resources, in addition to the local subsystem resources. This wiki article documents best-case access latencies for the AM57x PRU reading various SoC resources.

The PRU write instruction is a fire-and-forget command that executes in ~1 cycle. The PRU read instruction executes in ~2 cycles, plus additional latencies due to traversing through interconnect layers and variable processing loads. In general, MMRs that are "closer" to the PRU (i.e. within the PRU subsystem) will have lower access latencies.

The read latency values provided in this article are considered "best-case," accounting for the 2 cycle instruction and interconnect introduced latency. Note memory accesses outside of the PRU subsystem are not deterministic.

= PRU Read Latencies =

The following are considered "best-case" read latency values for the PRU on AM57x.

= PRU Data Transfer Latencies =

The following are considered "best-case" data transfer latencies for the AM57x PRU.