Talk:AM387x / C6A814x Schematic Review Checklist

Comments on AM387x / C6A814x Schematic Review Checklist -

D-smalley said ...
Booting issues –

1.	XIP Presence Detection behavior - BTMode[4-0] patterns which include XIP boot option may hang the ROM on the XIP boot stage if XIP device is not present because of method that ROM uses to detect whether a valid XIP image is present. During XIP boot stage the ROM reads data values at 0x8000:0000 and if it reads back any pattern other than 0000 or FFFF it concludes that a programmed XIP memory is present and it proceeds to branch to that address. The pin multiplexing is such that the ROM will often read a pattern other than 0000 or FFFF when XIP is not present so it will mistakenly branch execution to 0x8000:0000. In this case the ROM get caughts in a dead loop and requires a power-on reset to recover.

To avoid this lock-up situation on systems where XIP memory is not present there are two options a.	user can avoid using BTMode[4-0] patterns which include XIP in the boot order because the ROM code will not detect that XIP image is not present and drop through to the next device in the order. For example BTMode[4-0]=0001b indicates boot order of UART, then XIP w/WAIT, then MMC, then SPI. If this boot order is selected and XIP memory is not present, it will attempt UART boot. If that fails, it will go on to XIP boot mode and become stuck. The user will be constrained to use boot patterns which encounter a valid booting device prior to XIP booting phase. b.	User can place a data buffer on the GPMC data bus which ensures the GPMC_D[15:0] signals are driven to 0000 or FFFF during ROM execution so that the XIP boot will be skipped. After ROM completes, user code would need to configure GPMC_D[15:0] lines to normal operation prior to performing GPMC read or write.

2.	XIP boot GPMC High order address bit handling – As described in section 4.7.2.2 of the DM814x TRM, the ROM code does not multiplex high order address lines gpmc_a[27:13] to their address functions, although the external memory device generally needs to see logic "0" on its higher order address bits to correctly address memory. Many of the high order address pads default to internal pull-down active; however, some pins will default to internal pull-up active and therefore will need to be driven or pulled low by external hardware for the duration of XIP boot operation. See the device data manual for specific details. Then are two approaches to successfully perform XIP boot a.	Add external pull down resistors on GPMC lines which default to pullup so that the high order address lines will be logical 0 during ROM execution b.	Add an external mux on XIP memory address lines to force 0 state on high order address lines during ROM execution. Note that user code would need to control this mux in user code (via gpio control) before accessing GPMC address above 4KB. In both cases above the user code needs to re-mux the high order address lines appropriately within the first 4KB of execution (in code space where high order bits are supposed to be zero)

3.	MMC/SD. User should please note the following: a.	Centaurus has 3 instances of MMC/SD/SDIO controller (suffix 0,1 or 2). Booting is supported from MMC/SD/SDIO1 only b.	Centaurus ROM is incompatible with most eMMC devices which are >2GB. Sandisk makes a 4GB device which IS compatible with Centaurus ROM

--D-smalley 21:47, 13 June 2012 (CDT)

D-smalley said ...
DDR3

1.	Follow Layout recommendations in Data Manual section “DDR3 Routing Specifications” 2.	Vtt power supply must be capable of sourcing and sinking current (use active supply like TPS51200). See Data manual section on Vtt 3.	Centaurus DDR3 EMIF timing must be set to match DDR memory device data sheet timing parameters for particular device being used (including speed bin). An internal spreadsheet is available here http://ap-fpdsp-swapps.dal.design.ti.com/index.php/DM814x_Customer_Collateral_-_Internal_Page 4.	Because DDR3 address and Control signals use fly-by routing, a software controlled leveling process must performed. See procedure outlined here http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot. YOU NEED AN EMULATOR AND CCS4 or CCS5 to do this!

GPIO 1.	gp1[7,8,9,10] pins are also used for MLB peripheral (automotive optical interface) and there is another level of muxing to be set up. Enable these signals, ENLVCMOS, ENN, and ENP of MLBP_SIG_IO_CTRL register is required. This register address is 0x48140E18 for GPIO[7] and GPIO[8], 0x48140E1C for GPIO[9] and GPIO[10]. When I set to LOW, the voltage measurement is 0.01V and 1.8V when set to HIGH. Attached is my GEL file if you want to see on the EVM. These are the steps: GPIO_ClkEnable GPIO1_EnableLvcmosPadN_PadPReceiver GPIO_SelectGPIO_0and1_Pinmux GPIO1_OutputEnable_High  for HIGH 5.    GPIO1_OutputEnable_Low    for LOW

--D-smalley 21:49, 13 June 2012 (CDT)

D-smalley said ...
Here's a newer page with the DDR timing spreadsheet file http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

--D-smalley 13:22, 15 June 2012 (CDT)