AM3715/03 SDRC Subsystem

'''  Content is no longer maintained and is being kept for reference only! ''' The SDRC subsystem module provides connectivity between the AM37x and SDRAM memory components. The module includes support for low-power double-data-rate SDRAM (LPDDR1). The SDRC subsystem provides a high-performance interface to a variety of fast memory devices. It comprises two submodules:


 * SDRAM Memory Scheduler (SMS) consisting of scheduler and virtual rotated frame-buffer (VRFB) modules
 * SDRC

SDRAM Memory Scheduler (SMS)
The SMS optimizes the SDRAM memory usage to provide The QoS level required by each of the initiators in the system and also adds a rotation engine (VRFB) to minimize the SDRAM page-miss penalty when accessing rotated lines in a graphic frame buffer.

Features

 * VRFB module
 * Minimizes SDRAM page-miss penalty when accessing graphics buffer in nonnatural raster-scan order
 * Supports rotations of 0, 90, 180, and 270 degrees
 * Transparent to software applications – 12 concurrent rotation contexts
 * Memory-access scheduler
 * Optimizes latency and bandwidth usage between initiators
 * Per-system initiator group quality-of-service (QoS) control
 * 8 * 8 * 64 request queue FIFO for optimal scheduling
 * Programmable arbitration scheme
 * Focus on real-time memory processes (DSS display, camera interface)
 * Focus on MPU/DSP memory latency
 * Fair arbitration between other system initiators (DMAs, video subsystem, GFX accelerator)
 * Exclusive read-write transaction support

SDRAM Controller (SDRC)
The External Memory Interface (EMIF) is an Open Core Protocol (OCP) 2.2 compliant slave peripheral providing an interface to LPDDR SDRAM. The EMIF suooprts 16 or 32 bit data bus widths with 1GB of addressable space over 2 Chip Selects (512MB per CS). The SDRC bus supports a max of 2 loads.

Features

 * SDRAM Controller
 * Support for two independent CSs, with their corresponding register sets, and independent page tracking
 * Supports the following memory types: • Mobile Single Data Rate SDRAM (M-SDR) • Low-Power Double Data Rate SDRAM (LPDDR)
 * Memory device capacity: • 16 Mbits, 32 Mbits, 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, and 2 Gbits device support
 * Memory device organization • 2-bank support for 16 Mbits and 32 Mbits • 4-bank support for 64 Mbits to 2 Gbits • Flexible row/column address multiplexing schemes • Bank linear addressing • 16- or 32-bit data path to external SDRAM memory • 1G byte maximum addressing capability • Device driver strength feature for mobile DDR supported • New flexible address-muxing scheme lets users choose different bank mapping allocations by configuring the bank and column address decoding ordering.
 * Fully pipelined operation for optimal memory bandwidth usage
 * Burst support • Memory burst support • System burst for SDR SDRAM: system burst translated into memory burst of 2 • System burst for mobile DDR SDRAM: system burst translated into memory burst size of 4 • Read interrupt by read, write interrupt by write
 * CAS latency support 1, 2, 3, 4, 5
 * Fully programmable ac timing parameters (on a per-parameter basis). Parameters are set according to the memory interface clock frequency with respect to the attached memory device timing specifications.
 * Fine tuning of the controlled delay elements when operating with DDR memory
 * Dynamic endianness support
 * 9 × 64 bit lookahead FIFO in the SDRAM controller with a maximum of four transaction entries
 * Low-power management support • Dynamic power-saving features (internal clock gating) • Static power-saving features • Support for all standard low-power memory features • Support for enhanced low-power features (mobile devices) • Very low-power controlled-delay technology for optimal performance with DDR memory • Can operate with mobile DDR memory at very low clock rates
 * Autorefresh and self-refresh management

AM37x Hardware connections to SDRAM
This section will discuss the connections and recomendations for connecting to LPDDR1 memories. The AM37x SDRAM interface opperates at a maximum of 200MHz allowing connection to 400LPDDR1 devices. The interface supports 1GByte over 2 Chip Selects. The SDRC signals should never exceed 2 loads. Some memories increase capacity by stacking dies in their packages. Each die in the memory device adds a load to the SDRC signals, so if a memory has 2 dies in the device then the AM37x SDRC signals will have 2 loads present.


 * Please visit the AM37x Schematic check list for more details on designing in the AM37x.

LPDDR1
The figure below shows the SDRC subsystem interfacing with one 16- and one 32-bit LPDDR memories.

SDRC Registers
To set up the AM35x SDRC registers please visit the wiki link below. This link provides key registere descriptions as well as a tool for calculating the proper values for the SDRC timing registers.

AM37x SDRC registers

Schematics

 * Key care abouts (Power vs ground, DDR supply)
 * Clock and DQS routing info
 * Schematics for mDDR Interface
 * Routing Guidelines for mDDR

Software Design Support
Board Support Library files

Useful Links

 * Sitara E2E forums
 * Sitara ARM® product page
 * AM3715 Data manual
 * AM37x Technical Reference Manual (TRM) (GPMC section 10.1)
 * AM37x SDRC registers
 * Memory vendor wiki
 * AM37x Memory subsystem