AM57xx Schematic Checklist

= Introduction = The content of this page points to examples and documents that specifically reference AM572x devices. They are equally applicable to AM571x devices, AM570x devices and AM574x devices. Links for additional AM57xx product pages and reference documents will be added as they become available. This article applies to the following devices: Here are some links to some TI hardware designs based on AM57xx: '''Don't forget to check the relevant Sitara Processors Silicon Errata document when designing a board. This document will contain important information on silicon issues which will affect your board design.''' Also check these other useful links:
 * AM5726BABCX
 * AM5726BABCXA
 * AM5726BABCXAR
 * AM5726BABCXEA
 * AM5728BABCX
 * AM5728BABCXA
 * AM5728BABCXEA
 * AM5716AABCD
 * AM5716AABCDA
 * AM5716AABCDEA
 * AM5716AABCX
 * AM5716AABCXA
 * AM5716AABCXEA
 * AM5716AABCXEQ1
 * AM5716AABCXQ1
 * AM5718AABCX
 * AM5718AABCXA
 * AM5718AABCXEA
 * AM5718AABCXEQ1
 * AM5718AABCXQ1
 * AM5706BCBDD
 * AM5706BCBDDA
 * AM5706BCBDDEA
 * AM5706BCBDJ
 * AM5706BCBDJA
 * AM5706BCBDJEA
 * AM5708BCBDJ
 * AM5708BCBDJA
 * AM5708BCBDJAR
 * AM5708BCBDJEA
 * AM5708BCBDJEAR
 * AM5708BCBDJR
 * XAM5708BCBDJEA
 * XAM5746ABZXEA
 * XAM5748ABZXEA
 * AM572x General Purpose EVM
 * AM572x Industrial Development Kit EVM
 * AM571x Industrial Development Kit EVM
 * DRA71x/AM570x EVM
 * AM570x 6-Layer PCB Reference Design
 * AM574x Industrial Development Kit EVM
 * AM572x Sitara Processors Silicon Errata
 * AM571x (SR 2.0, 1.0) and AM570x (SR 2.1, 2.0) Sitara Processors Silicon Errata
 * AM574x Sitara Processors Silicon Silicon Errata
 * AM574x/AM572x/AM571x Compatibility Guide
 * High-Speed Interface Layout Guidelines
 * AM57xx BGA PCB Design
 * AM57xx PCB Escape Routing Guidelines
 * TI PinMux Tool

= Recommendations Specific to AM57xx =

EVM vs Datasheet
In case of any discrepancy between the TI EVMs and the device datasheet, always follow the datasheet. Despite the designer's best efforts, the EVMs may contain errors which may still function but are not completely aligned with the datasheet specification. Therefore the EVM designs should not be considered as reference designs to be blindly reused.

Power
Be sure to connect a 2.2uF capacitor between the OSC16MCAP pin and ground as required when using the TPS659037x PMICs recommended for AM57xx devices.
 * AM57x family of devices mandates use of specific PMIC family. Please check the device specific data manual to see which PMIC needs to be used. You can also refer to the table above for the AM57x family to PMIC part mapping
 * Check that the correct voltages are applied to the correct power pins on the chip and that the required current can be supplied.
 * Zero ohm resistors in line with core and other power sections of the board are recommended for initial PCB prototype builds if the user wants to measure power. The user should then remove the resistor in production builds and connect the power planes with wide copper or multiple vias. Power measurement is the purpose of these resistors in the EVM designs. Note that the implementation of these resistors adds inductance and resistance that can impair power supply and power distribution performance.
 * Proper power supply sequencing in proper correlation with resets and clocks is required. Please refer to the device specific datasheet for the recommended power sequencing requirements.
 * A TI smart reflex solution is required for the VDD, VDD_MPU, VDD_GPU, VDD_IVA and VDD_DSPEVE rails of AM57xx devices. Using smart reflex reduces device power consumption and ensures the proper operation across the temperature range. AM57xx devices are used with PMIC power controllers such as those in the TPS659037x family which support the recommended smart reflex implementation. Supported PMIC companion devices are referenced in the AM57xx Data Manual.
 * Each of the VDDA_xxxxx power input pins should be connected to V1_8D through a filter circuit. In some cases, a single filter may used for multiple pins.
 * The DDR3 interface requires a VTT termination at the end of the flyby chain for the DDR3 address, command, control and clock signals. The VTT termination voltage is generated using a special push/pull termination regulator specifically designed to meet the VTT requirements for DDR3.
 * The VTT regulator can provide the voltage rail for the DDR reference voltage also. If not, a voltage divider using tight tolerance (1% or better) resistors can be used. If a resistor divider is used, the VREFSSTL source voltage MUST be generated from the VDDS_DDR supply so that it tracks that supply.
 * AM57xx devices contain multiple analog power pins that provide power to sensitive analog circuitry like PLLs, DLLs and SERDES buffers and terminations. These must be attached to filtered power sources. These filter solutions must match the recommendations in the Hardware Design Guide.
 * The AM57xx EVM is configured to power up after the user presses the power button. If you instead prefer the board to start as soon as power is applied, please see this FAQ.
 * The internal LDO regulators on the AM57xx device require external capacitors connected to their output pins (CAP_VBBLDO_MPU1, CAP_VDDRAM_DSPEVE1, CAP_VDDRAM_CORE2, etc.). Be sure to place a 1uF capacitor from each of these LDO outputs to ground (VSS).  See the AM57xx Data Manual for the list of LDO outputs.  These capacitors must be placed as close to the respective pin as possible (within 0.25" of the package boundary).
 * Ensure current capabilities of DC/DC switchers and LDOs meet the maximum demand of all devices that are attached. You can find the maximum current draw of all AM57xx I/O rails in the datasheet. If these rails from the PMIC also power other devices, the maximum current draw of these devices need to be taken into consideration as well.
 * The PMIC will control the supply sequencing so that it meets the requirements of the AM57xx device during start-up. It will also properly control the sequencing during shut-down as long is it is properly powered during this period.  A detect circuit such at a TPS3808 can monitor the main supply input and initiate the shut-down sequence when the main supply starts to drop by driving the RESET_IN to the PMIC.  Sufficient capacitance will be required to hold up the main supply to the PMIC for at least 1.1ms after RESET_IN is driven low for the sequence to complete.
 * Ensure I2C1 is used for communication to PMIC. All TI software distributions (linux SDK) assume the use of this interface with the PMIC.
 * The LVCMOS Input/output pins powered from the VDDSHVxx supplies support both 3.3V and 1.8V nominal power supplies. During power-up, operation and power-down, the VDDSHVxx supplies set at 3.3V nominal cannot be more than 2.0V above the vdds18v supply voltage.  This is shown in figure 5-3 of the Data Manual.  A voltage clamp circuit may be needed to guarantee this restriction is met.  An example of this circuit can be found in Section 6 of SLVU731.  This is not required for 3.3V supplies derived from LDOs or SMPS9 of the TPS659037x PMIC.  This circuit will be required if using a 3.3V supply enabled through a power switch that is controlled by REGEN1 unless you can prove that the shut-down sequence will be met.
 * Be sure to use low ESL capacitors and to mount them with short traces to keep the mounting inductance very low. This is required to meet the specificed PDN impedance.  Please see Application Report SPRAC76 Sitara Processor Power Distribution Networks: Implementation and Analysis for more detail.
 * PMIC SMPS converters have “remote sense” or SMPSx_FDBK inputs. These must be connected at the load (or even the far side of the load), not at the PMIC output. The IR drop in the power distribution routing can result in the load not getting sufficient voltage. A 0-ohm resistor can be put at the end of each of these traces to enforce the routing to the proper sense point.
 * Refer to TPS659037 Design Guide document designed to aid customers designing with the TPS659037x family of PMICs.
 * Refer to TPS659037 Design Checklist tool designed to aid customers designing with the TPS659037x family of PMICs.
 * Refer to the TPS659037 User's Guide to Power AM572x and AM571x for detailed recommendations on connecting and routing.

Reset
If you're using the PMIC feature to workaround errata i862, make sure you do not have a pullup on RSTOUTn as it will cause an infinite reboot loop.
 * The hard reset PORZ is best if driven from power good circuitry to assure proper sequencing such that power is stable and input clock signals are stable before PORZ is released. Check the data manual for details about the requirements of PORZ.
 * Reset pins must be driven as defined in the device’s Data Manual. This sequencing in relation to clocks and power supply ramping must be followed in all operating conditions, including boundary scan testing.
 * PORZ must be held low until all supplies have been stable for some time. Conversely, PORZ must be pulled low before any supply rails begin power down - especially in any unexpected power-loss situations.
 * The PORZ pin has special properties such that it holds all output pins at high impedance when low. When controlled from logic derived from a Power Good indication, it can safely shut down the device and prevent output contention if a power supply fault occurs.
 * All control pins must be held at the proper input level prior to the reset signal rising that releases the device from reset.
 * RSTOUTn is driven low whenever the device enters the reset state. RSTOUTn is undefined during supply ramp. Ensure peripheral reset inputs can handle this. If there is sensitivity, add a 100 ohm resistor in series before sending RSTOUTn to peripheral circuits. Check EVM schematic for an example.
 * There is an erratum that requires all reset events to trigger a PORz - i862 Reset Should Use PORz. This can be implemented through an external PORz pulse generator as shown on the GP EVM or implemented using a feature of the PMIC as shown on the IDK EVM.  Both solutions are valid but result in design tradeoffs.  This is documented in detail in the Errata document under i862.

Boot Modes

 * SYSBOOT pins must be properly configured to set the proper boot mode at reset release. These can be set by resistor population or driven from logic such as an FPGA.
 * SYSBOOT15
 * AM574x
 * SYSBOOT15 is configurable. In short, it should be pulled high if booting from eMMC and pulled low for booting from parallel NOR flash.  For complete details, please see the AM574x TRM Section 18.4.6.1.1.1 "Permanent PU/PD disabling".
 * AM572x
 * For Silicon Revision 1.x, SYSBOOT15 must be tied to VDD.
 * For Silicon Revision 2.0, SYSBOOT15 is configurable. In short, it should be pulled high if booting from eMMC and pulled low for booting from parallel NOR flash.  For complete details, please see the AM572x TRM Section 18.4.6.1.1.1 "Permanent PU/PD disabling (SR 2.0 only)".
 * AM571x
 * For Silicon Revision 1.0, SYSBOOT15 must be tied to VDD.
 * For Silicon Revision 2.0, SYSBOOT15 is configurable. In short, it should be pulled low if booting from eMMC and pulled high for booting from parallel NOR flash.  For complete details, please see the AM571x AM570x TRM Section 18.4.6.1.1.1 "Permanent PU/PD disabling (SR 2.x only)".
 * AM570x
 * For Silicon Revision 2.1, SYSBOOT15 is configurable. In short, it should be pulled low if booting from eMMC and pulled high for booting from parallel NOR flash.  For complete details, please see the AM571x AM570x TRM Section 18.4.6.1.1.1 "Permanent PU/PD disabling (SR 2.x only)".
 * If the SYSBOOT pins are redefined for another purpose during operation, they must be released and set back to the proper levels to select the boot mode whenever PORz goes low and they must remain unchanged for the defined hold duration after PORz rising per the Data Manual.
 * SYSBOOT14 must be tied to VSS.

Unused Signals
Signals on interfaces that are unused can typically be left as no connect. Many of the IOs have a Pad Configuration Register (see the Control Module chapter of the TRM for more details) which gives control over the input capabilities of the I/O (INPUTENABLE field in each conf_&lt;module&gt;_&lt;pin&gt; register). Software should disable the receivers I/Os which are no connects (ie, INPUTENABLE=0) as soon as possible during initialization. This INPUTENABLE field defaults to "input active" for most signals, which means there is a potential for some leakage during powerup of the chip if the input floats to a mid-supply level before the software can initialize the I/O. This should only be a concern if you are attempting to power up the design with a minimum power consumption. Most designs should be able to tolerate this small amount of leakage in each floating I/O until the software has a chance to disable it. After disabling the receiver of the I/O, no leakage will occur. Refer to section 4.1 in the Data Manual for specific guidance on certain unused pins.

Unused OSC1
If OSC1 is unused, be sure that the xi_osc1 pin is grounded or pulled low.

If DDR1 is not used

 * Connect the VDDS_DDR1 terminals to either 1.35V or 1.5V.
 * Connect the VDDS18V_DDR1 to 1.8V
 * Connect the DDR1_VREF0 to 0.5*VDDS_DDR1

If DDR2 is not used

 * Connect the VDDS_DDR2 terminals to either 1.35V or 1.5V.
 * Connect the VDDS18V_DDR2 to 1.8V
 * Connect the DDR2_VREF0 to 0.5*VDDS_DDR2

If USB1, USB2, or USB3 are not used

 * Connect the respective VDDA_USB1, VDDA_USB2, VDDA_USB3 terminal to any 1.8-V power supply and respective
 * VDDA33V_USB1/2
 * AM572x/AM571x: Connect VDDA33V_USB1 or VDDA33V_USB2 terminal directly to any 3.3-V power supply. No decoupling is required in this case. If the system does not have a 3.3-V power supply, these terminals may be connected to ground.
 * AM570x: The VDDA33V_USB1 or VDDA33V_USB2 terminal must be connected to a 3.3V power supply since this rail also powers digital IO buffers.

If HDMI is not used

 * VDDA_HDMI should be connected through a ferrite bead to V1_8D

If PCIe is not used

 * VDDA_PCIE, VDDA_PCIE0, VDDA_PCIE1 should be connected to V1_8D through a common ferrite bead.

If SATA is not used

 * VDDA_SATA should be connected to V1_8D through a ferrite bead.

If RTC internal oscillator is not used
This can be the case when either the internal system clock is used or a 1.8 volt LVCMOS clock source is used rather than a crystal circuit or the RTC is not used at all. If a 1.8 volt LVCMOS clock source is used then: If no crystal oscillator or LVCMOS clock source is used then: If the RTC is not used, see RTC section below
 * Connect the clock source to the RTC_OSC_XI_CLKIN32 terminal
 * Leave the RTC_OSC_XO terminal open-circuit (floating)
 * Connect VSS_RTC to VSS
 * Connect the RTC_OSC_XI_CLKIN32 terminal through a puill-down resistor to VSS
 * Leave the RTC_OSC_XO terminal open-circuit (floating)
 * Connect VSS_RTC to VSS

Pull-up Resistors

 * Ensure all pullups connected to AM57xx device are pulled up to the correct I/O voltage to avoid any leakage between the I/O rails of the device. Each terminal has an associated supply voltage used to power its I/O cell. This can be found in the AM57xx Data Manual, in the Ball Characteristics table. For example, if you want to pull up terminal SPI1_CS1 in any mux mode (spi1_cs1, sata1_led, spi2_cs1, gpio7_11, etc.), it must be pulled up the signal to VDDSHV3.

Peripheral clock outputs

 * Put 22ohm series resistors (close to processor) on the output clocks of the following modules: MMC, GPMC, McASP (both clock and frame sync), SPI, QSPI and VOUT

General Debug

 * Output clocks CLKOUT1, CLKOUT2, and CLKOUT3 are present on several of the pins. If these pins/signals are not used in your design, it is good to have test points on these signals to be able to monitor internal clocks to support hardware and software debugging.

Low Power considerations
If you are designing for low power, here are some tips to help you optimize your design for low power:


 * On early prototype boards, it is recommended to include small shunt resistors in the voltage rail paths of each of the following power rails of AM57xx device: VDD_MPU, VDD, VDDS_DDR1, VDDS_DDR2, VDD_DSPEVE, VDD_IVA, VDD_GPU, VDDSHV1-11. These are listed in order of priority so if you can't isolate then add all of these to measure power, the most important ones are the core rails VDD_MPU, VDD, VDD_GPU, etc. Also, the VDDSHVx supplies may be broken into multiple segments and may be run at different voltages (VDDSHV8 for the microSD card can switch 3.3V/1.8V mode at run-time but the others cannot). This will help you measure the power consumption of each rail and potentially pinpoint high power consumption during development. You may also want to add these shunt resistors for power supplies connected to other devices to be able to measure power on those key devices. The AM57xx EVMs have examples of these shunt resistors.


 * For production, these shunt resistors must be removed from the design (i.e. turned into a continuous plane) since these resistors restrict current flow and add inductance to the PDN.

Clocking

 * If you do not need the RTC timer feature, you do not need to include a 32KHz crystal. The 32KHz reference can come from the high frequency clock or onboard RC oscillator. RTC_OSC_XI_CLKIN32 should be connected to VSS. Leave the RTC_OSC_XO pin not connected (floating). See RTC section for more details.
 * When using an external crystal, connect VSS_OSC to board ground.
 * It is preferable to always have bias and dampening resistors that can help tune the crystal later. See Section 6.1 Input Clock Specifications of the device datasheet for more details.

DDR3

 * It is very important to follow the DDR3 routing guidelines in the AM57xx device datasheet. These guidelines are very important to ensure a proper DDR3 operation.
 * When using a resistor divider for DDR_VREF, ensure resistors are high precision resistors (1% or better) as specified in the datasheet.
 * Provide adequate decoupling capacitors on the DDR power rails both at the AM57xx device as well as at the DDR SDRAM device(s). Proper distribution of these capacitors is mandatory when referencing fly-by signals to VDDS.
 * Designs with point to point connections between AM57xx device and a single DDR3 SDRAM typically do not need VTT termination although this may be needed depending on the specific PCB characteristics. For multiple device topologies or multi-die packages, VTT termination is required. A VTT termination regulator is required for properly terminating the address, command and control fly-by signals. Check datasheet and/or reference schematic for proper connection. The TPS51200 is recommended for use as the VTT termination regulator.
 * Do not connect DDR_RESET to VTT termination resistors. DDR_RESET should be connected directly between the AM57xx device and the SDRAMs. Addition of a pull-down resistor is also recommended.
 * Check datasheet for proper termination voltages. Termination for the fly-by clock signals is to VDDS_DDR1 and VDDS_DDR2 (through termination resistors to a balancing coupling capacitor), whereas all other fly-by signals need to use terminations resistors connect to VTT for the termination voltage. Refer to the device datasheet for details.
 * VREF can be obtained from the VTT termination regulator or from a resistor divider (2.2Kohm 1% resistors) with capacitive decoupling to ground. It will be used as references for both CA and DQ pins on the memory, as well as the VREF signal on the AM57xx device. Ensure resistors are a high precision (1% or better) resistors as specified in the datasheet. Be sure to carefully follow the VREF routing guidelines in the datasheet.
 * ECC is supported on EMIF1 but its use is currently limited to specific implementations. Please see the errata document for more details.
 * Data bit swapping within the data byte is allowed. The PHY is implemented such that this does not impact leveling.  Bit swapping is not allowed for any other group of signals, including ADDR and CNTL.
 * Address mirroring (as defined in JEDEC DDR3 documentation) is not supported on this device. The Data Manual refers to a mirrored placement which means that SDRAM devices can be mounted on both top and bottom.  This is allowed as long as the routing rules are still met; which takes significant care.  The mirrored placement in the Data Manual does not mean that 'address mirroring' is supported.
 * If a particular DDR interface is not used, then the applicable DDRx_DQSn and DDRx_DQSNn pins should be tied to the appropriate GND or power through a 1Kohm resistor to keep the signals inactive as stated in the Data Manual. The same is also required if only a single byte lane is unused, such as the ECC byte lane. The address, command, control, clock and data lines can all be left floating. The DDR supplies and VREF must be maintained at their rated levels per the Data Manual.

MMC

 * Include a 22ohm series resistor on MMCx_CLK (as close to the processor as possible). This signal is used as an input on read transactions and the resistor will eliminate possible signal reflections on the signal which can cause false clock transitions.
 * Pull-up resistors are needed on all data signals and on the command signal. These pullups should be 10K ohms for SD-CARD implementations and 49.9K ohms for embedded device connections, such as eMMC memory devices.
 * To support the UHS-I speeds on MMC1,
 * You need a dedicated, configurable LDO connected to VDDSHV8. The EVM uses the LDO1 output from the PMIC.
 * Do not use this LDO to power anything else on the board since it will change dynamically at run-time.
 * The SD card's VDD signal should be connected to a fixed 3.3V rail. In other words, the card's VDD must remain at 3.3V even for the UHS-I modes of operation.  Only the signaling levels change in these modes, not VDD.
 * Pullups on the SD/MMC signals should go to the LDO rail such that their voltages coincide with the mode of operation.

I2C

 * Pull-up resistors must be attached on both I2C signals (I2C_DATA and I2C_CLK) and should be 2.2K. Ensure the pull-up resistors connect to the correct I/O voltage rail. See note on Pull-up Resistors section above.
 * If you are planning to use TI's software (Linux SDK), be sure to connect I2C1 to the PMIC, as this is the port used for PMIC control.
 * I2C1 and I2C2 use true open drain buffers that are fully compliant to the I2C specifications. These support 100 kHz and 400 kHz operation.
 * I2C3/4/5 use LVCMOS to emulate an open drain buffer. These can support 3.4 Mbps I2C operation. These ports are not fully compliant with the I2C specs.  In particular the falling edges are too fast (<2ns).  Any devices connected to these ports must be able to function properly with this fall time.

QSPI

 * Make sure SCLK is looped back at the board level to RTCLK in order to leverage the faster mode 0 timings.
 * Be sure that d0 of the QSPI peripheral connects with d0 of the memory. The initial communication occurs only over d0 and the interface won't work if these are mis-mapped.
 * Follow the layout guidelines in the data manual.

NAND

 * Typically the R/B# signal from the NAND is open drain and connected to the AM57xx GPMC_WAIT signal. Be sure to include a 4.7K pullup to the appropriate voltage, depending if the NAND is 1.8V or 3.3V.

VOUT

 * VOUT3 on AM572x devices must only be operated at 1.8V when it is multiplexed onto the VIN1A pins in the VDDSHV6 power domain. Alternately, use VOUT3 at 3.3V when it is multiplexed onto the GPMC pins in the VDDSHV10 power domain.  Please refer to the AM572x Sitara Processors Silicon Errata for more information.


 * VOUT1, VOUT2 and VOUT3 on AM571x devices must only be operated at 1.8V. Please refer to the AM571x (SR 2.0, 1.0) and AM570x (SR 2.0) Sitara Processors Silicon Errata for more information.


 * VOUT1, VOUT2 and VOUT3 on AM570x devices may be operated at 3.3V or 1.8V without restriction.

USB

 * Refer to the High-Speed Interface Layout Guidelines Application Report for detailed recommendations for proper USB signal connection and routing.
 * For USB Device operation, USB VBUS decoupling capacitance should be &lt; 10uF.
 * For USB Host operation, USB VBUS decoupling capacitance should be &gt; 120uF.
 * Ensure the VBUS decoupling capacitance is connected close to USB connector.
 * USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points.
 * Typical connections of the AM57xx for a USB Device:
 * USBx_DP and USBx_DM are connected directly to the USB connector
 * Connector ID pin can be left unconnected
 * USBx_DRVVBUS is not used and can be left unconnected
 * Typical connections of the AM57xx for a USB Host:
 * USBx_DP and USBx_DM are connected directly to the USB connector
 * Connector ID should be grounded
 * USBx_DRVVBUS should be connected to the enable of the 5V VBUS power source
 * Connector VBUS should be connected to the output of the 5V VBUS power from the power switch by USBx_DRVVBUS
 * Typical connections for a USB Host with USB hub:
 * USBx_DP and USBx_DM are connected directly to the USB hub upstream port (hub then distributes these signals to the downstream ports as needed)
 * Connector ID should be grounded to enable host mode
 * USBx_DRVVBUS should be unconnected
 * USBx_VBUS should be connected to the output of the 5V VBUS power source. It is also connected to the VBUS detect on the hub, which then allows the hub to selectively enable/disable typically through a power switch to each downstream port.
 * Common-mode chokes may be needed for EMI/EMC control. Note that these may reduce the signal amplitude and degrade performance.

Ethernet

 * No series resistors are required for MII signals. They may be implemented on the clock signals if the routes are long or through a connector.
 * For the RGMII interfaces, 22 ohm series termination resistors must be placed on all 12 interface signals as close to the transmitting I/O a possible. Be sure to check voltage compatibility between the AM57xx I/O and the Ethernet PHY I/O.

RTC
The following table describes what to do with each pin related to RTC functionality. Two use case scenarios are provided:
 * RTC timer functional: If you will be using the RTC feature, this use case allows you to use the Real Time Clock features (eg, keeping time).
 * RTC feature disabled: If you will never use the RTC features, the RTC functions are fully disabled.

 Note 


 * 1) If using an external LVCMOS input for the 32kHz clock, it must be amplitude of VDDA_RTC since this pin is related to VDDA_RTC power domain.
 * 2) RTC_ISO, RTC_PORZ and the WAKEUPx signals are all on the VDDSHV5 power domain. Since the VDDSHV5 power domain can be either 1.8V or 3.3V, nominal, these signals must be driven from sources of the matching VDDSHV5 level.
 * 3) PORZ is on the VDDSHV3 power domain. The recommendation to connect RTC_ISO to PORZ is valid only if VDDSHV5 and VDDSHV3 are powered by equal voltage levels (3.3V or 1.8V). Alternately, when unused, RTC_ISO can be pulled up to VDDSHV5. Similarly, if PORz and RTC_PORz are at different voltages, appropriate level versions of each will need to be provided.
 * 4) WAKEUPx pins that are configured for other pinmux options do not need to be terminated per this table.  These recommendations are for when they are configured for WAKEUP pin functionality.

JTAG and EMU

 * Clock and signal buffering are required whenever the JTAG interface connects to more than one device. Clock buffering is strongly recommended even for single device implementations. Verify series terminations are provided on each clock buffer output and ideally, that the clock output tracks are skew matched.
 * EMU pins must not be buffered. EMU[1:0] can be bussed to multiple devices. Other EMU pins connected for trace usage must be short and skew matched.
 * For more recommendations on EMU routing, refer to Emulation and Trace Headers Technical Reference Manual.
 * Similarly, a summary of this information is available at XDS Target Connection Guide.
 * Adaptive clocking must be implemented correctly using the RTCK output.
 * If the JTAG and EMU interface is not used, all pins except TRSTn, TCK and TMS can be left floating. TRSTn must be pulled low to ground through a 4.7kΩ resistor. TCK and TMS must be pulled to VDDSHV3 through a 4.7kΩ resistor. However it is strongly recommended that all board designs contain at least a minimal JTAG port connection to test points or a header footprint to support early prototype debugging.  The minimum connections are TCK, RTCK, TMS, TDI, TDO and TRSTn. JTAG routes and component footprints (except the PD on TRSTn and the PU on TMS and TCK) can be deleted in the production version of the board, if desired.
 * In the event that the JTAG interface is used and the EMU interface (or a subset of the emulation pins) is not used, the unused EMU pins can be left floating.

PCIe

 * Refer to the High-Speed Interface Layout Guidelines Application Report for detailed recommendations for proper USB signal connection and routing.
 * DC blocking caps are needed on the reference clock input.
 * DC blocking capacitors are required for data lanes and should be implemented on the TX end.

GPIO
There are some GPIO pins that are input-only:
 * gpio1_0
 * gpio1_1
 * gpio1_2
 * gpio1_3
 * gpio8_27