AM35x Schematic Checklist

'''  Content is no longer maintained and is being kept for reference only! '''

= Introduction =

This page applies to the following devices:
 * AM3517
 * AM3505

Here are some links to schematics you can refer to:

AM35x SOM (System on Module) from LogicPD Craneboard open source design

= Recommendations Specific to AM35x =

Power

 * If using TPS659xx devices, please refer to the following app notes for more information on schematic and layout recommendations:
 * SWCA073
 * SWCA076
 * SWCU056
 * SWCU055


 * Check decoupling capacitors (refer to the appropriate Data Manual for your device). Recommend 1 capacitor per 2 to 4 balls.
 * VPP : should be left unconnected for production
 * If using TPS6595x PMIC, SYS_CLKREQ should be connected to TPS6595x CLKREQ. SYS_CLKREQ signal polarity is programmable using PRM_POLCTRL register, so ensure your external hardware matches the intended use of this signal.


 * If using TPS65023, refer to the TPS65023 Design-In Wiki
 * If using TPS65073, refer to the TPS65073 Design-In Wiki
 * If using TPS65910, refer to the TPS65910 Product Folder

RESETS
-Need to add an open-drain buffer to warm reset. (Please see AM35x EVM schematics for an example). Also, ensure you put an 4.7K pullup (at the output of the buffer) Here is the reason for the buffer:

1. SYS_NRESWARM is pulled-low when SYS_NRESPWRON is LOW. 2. Once SYS_NRESPWRON goes HIGH, for PRM_RSTTIME, SYS_NRESWARM will be driven LOW (No pull down). 3. After that SYS_NRESWARM will be pulled high internally.

On the EVM, the initial pull down from AM3517 is fighting with the internal pull up on the 8710 (Ethernet PHY), causing a voltage divider. In most cases, the LAN8710 was actually seeing a high voltage, meaning it was out of reset and trying to link at 100Mbit full duplex. Upon SYS_NRESPWRON going high, the 8710 would see another low then high on the its reset. This pulse actually ends up being too short, and the 8710 would drop back into 10Mbit half duplex mode.

The buffer was put in there to ensure the reset to the LAN8710 (and to other devices) would be driven low the entire SYS_NRESPWRON time + PRM_RSTTIME. This also allows the mode pins on the Ethernet PHY to be latched properly on reset.


 * Typically, warm reset is used for a push button reset or reset from external circuits. However, be aware that warm reset does not follow the same boot up sequence that a power on reset performs.  If you want a reset that will be following by the boot order you establish for power on reset, you must use SYS_NRESPWRON.

Clocks

 * For the High Frequency clock, AM3505/17 can only support 26MHz crystal or oscillator input.
 * 26MHz oscillator must be 50ppm or less.
 * The 32KHz clock can be obtained externally (connect a 32KHz oscillator), or can be derived from the 26MHz clock if you want to reduce the BOM cost of a 32KHz oscillator. Note that the internally generated 32K is not accurate (~32.5K), so it cannot be used as a accurate source for internal timers.
 * ensure that the startup time for both oscillators is shorter than the SYS_NRESPWRON delay time. Both clocks must be stable before SYS_NRESPWRON is released.
 * When using a 26MHz crystal for the high frequency clock, connect the crystal case ground and associated load caps to VSSOSC only (not to board ground). Also add option to connect to board ground through 0 ohm resistor.  This will give you the option to connect to board ground at one point if needed.

Pin States

 * Check reset states of AM35x pins connected to other devices. AM35x pins may have inadvertent states at or right after reset which may conflict with external devices.  This information can be found in the AM35x Data Manual "Ball Characteristics" table.  Check the columns Ball Reset State, Ball Reset Rel. State, and Reset Rel. Mode.

Booting

 * Note that if you are looking to boot from UART, only UART3 can be used for booting (You cannot boot from UART1 or UART2). Also, UART3 is used for terminal debug.  It is recommended that you connect a transceiver to this port (check EVM schematics for reference)
 * For normal operation Please ensure sys_boot8 pin is pulled down.

Layout Guidelines
These are generic layout guidelines for BGA packaging: BGA PCB Design Guidelines BGA Decoupling Capacitor Guidelines

I2C

 * Pull ups on SDA and SCL. 4.7K can be used. When implementing high speed I2C, lower values (470ohm) should be used.

GPIO

 * The following GPIOs are input only: GPIO99,100,112,113,114. All other GPIOs are IOs.

MMC interface

 * MMC_CLK : no pull ups needed
 * MMC_CMD, MMC_DATx : 10K pull ups needed on each signal, unless using it in SDIO mode (eg., connected to a WLAN device) . Be sure to pull up to MMC voltage (VDDSHV).
 * MMC1_CLK, MMC2_CLK and MMC3_CLK, series resistor is needed, place as close to AM35x as possible. Recommended value is 33ohm, but will need to be adjusted based on trace length to the MMC peripheral.
 * If using MMCx_WP (write protect) and MMCx_CD (card detect) signals, they would typically be pulled up to VDDSHV before connecting to the processor GPIO.

TV OUT interface
Refer to the [[Media:TV_out_application_note.pdf|TV out Application note]]. This app note is applicable to AM35x family of devices.
 * Note that inductors on TVout circuit should be 3.3uH. Some AM35x schematics have them as 3.9nH, which is a typo.

DSS

 * refer to the Display Subsystem wiki for guidance on connecting the DSS.
 * add 10ohm series resistors to all data lines, HSYNC, VSYNC, ACBIAS, PCLK
 * Remember that AM3505/17 does not have data lane shifter like OMAP35x and if 8 bit YCbCr data is used you would need to shift 8 bits up to 8 MSBs. Only way to get 8 bit data piped through is by using Alaw compression which caused CbCr offset resulting in a greenish tint issue with TVP5146 8 bit data on AM35x EVM.  The following wiki article explains the change needed on the EVM: Errata

GPMC

 * check to make sure any pullups for WAIT signals are pulled up to VDDSHV.
 * if used, ensure GPMC_CLK has 33ohm series resistor placed close to AM35x

McBSP

 * Some McBSPs have different sized internal FIFOs. McBSP2 has 5K FIFO (others have only 512 bytes).
 * McBSP2 and McBSP3 have sidetone capabilities.
 * Place 33ohm series resistor close to AM35x on all McBSP clock signals

USB OTG

 * for OTG operation, USB VBUS decoupling capacitance should be 1-6.5uF
 * for device operation, USB VBUS decoupling capacitance should be &lt; 10uF. Leave USB0_DRVVBUS and USB0_ID as no connect.
 * for host operation, USB VBUS decoupling capacitance should be &gt; 120uF
 * ensure the VBUS decoupling capaciance is connected close to USB connector.
 * ID signals should not be pulled down with a pull down resistor. If defaulting to an A-device, ground the ID signal on the USB PHY.
 * ensure VBUS from the USB connector is connected to AM35x USB0_VBUS signal. Additionally, a charge pump or other power source needs to be connected to VBUS intending to use USB host mode, as it would need to provide proper power to downstream peripherals.

USB Host ports (HSUSB1 - HSUSB3)

 * HSUSB3 will only support FS/LS USB PHYs.
 * Review the Errata for issues concerning USB Host ports.
 * For USB Host ports (USB1 and USB2), we recommend using TI's TUSB1210 USB PHY. This PHY supports input clocking mode (ie, the PHY is in slave mode and OMAP35x sources the 60MHz ULPI clock). This device has recently been released.
 * It is not recommended to use the SMSC3320 if you are planning to use the USB suspend feature due to an specific interoperability errata with this device (refer to the AM35x errata). If using a SMSC332x PHY, it is recommended to supply the 1.8V to the PHY with a separate low noise power source.
 * The TUSB1210 and SMSC3320 are pin-for-pin compatible, with some minor modifications. If you want to design your board to accomodate both, please see the [[Media:OMAP3EVM_REVG_mods_to_use_TUSB1210.zip|following schematic]], which details the changes that need to be made to the OMAP3EVM to change from the SMSC332x to the TUSB1210.

DDR2

 * ensure that you follow the recommended layout guidelines and series termination values in section 6.4.2 of the AM35x Data Manual. Termination on AM35x outputs should be close to AM35x.  Termination on Bi-Directionals should be close to memory.  Ensure termination across net classes are the same value.
 * ensure the resistor divider circuit for VREF contains 1% precision resistors
 * ensure the resistor for DDR_PADREF is 50ohm / 1% precision

Ethernet

 * RMII requires 50ppm crystal
 * 1.5K pullup is recommended on RMII_MDIO_DATA
 * The AM35x EVM uses SMSC LAN8710 for the Ethernet PHY. Although the LAN8720 looks to be a better option, as it is RMII only (AM35x only supports RMII), and it only needs a 25MHz crystal (usually cheaper than a 50MHz oscillator), we do not recommend this device as it operates outside the RMII spec, and will violate timing relative to AM35x.  Check the SMSC website for more details.
 * Ethernet TXP/TXN/RXP/RXN lines should be routed as 100 ohm differential pairs with matched trace lines.
 * Ensure minimal stubs when adding resistors or capacitors off of TXP/TXN/RXP/RXN signals.
 * If your system requires ethernet boot, ensure that the Ethernet PHY is initialized properly (ie, it is out of reset and clock is stable) before the AM35x ROM code executes (ie, before SYS_PWRONRST deasserts). The ROM expects the PHY to be ready because it sends out a broadcast packet to initiate the ethernet boot.  If the PHY isn't ready, it won't send out the packet and the ethernet boot will fail.  One recommendation is to delay the reset signal going to SYS_NRESPWRON with some sort of RC circuit or buffer, long enough to for the PHY to come out of reset and initialize (this time should be specified in the PHY datasheet).  If you need to separately reset the PHY during normal operation, you can add an AND gate to add control from an AM35x GPIO.
 * when configuring the mode bits on the ethernet PHY, ensure that those signals will be in the correct state when the PHY reset is deasserted (this is when they are typically latched). Check the reset state and reset release state in the AM35x datasheet for these signals to ensure external pull up/downs do not conflict with the state of these signals before and after SYS_PWRONRST.   Typical pull up/down drive strengths are 100uA.

McSPI

 * place series resistor close to AM35x on all MCSPI clock signals.

What to do with unused Power signals

 * VDDA_DAC: if signals powered by VDDA_VDAC are not used, tie to ground.


 * VDDA3P3V_USBPHY: if USB0 OTG is not being used, tie to ground.
 * VDDA1P8V_USBPHY: if USB0 OTG is not being used, connect to 1.8V supply.
 * CAP_VDDA1P2LDO_USBPHY: if USB0 OTG is not being used, a cap is not required. Keep the pin floating. Don’t ground this.

All other power rails should be powered at all times.

TV Output
When the TV output is not required then the following configuration should be implemented in order to reduce the power consumption to its minimum value.

The analog pins tv_vref, vssa_dac, VDDA_DAC, tv_out1/2 and tv_vfb1/2 should be grounded.

To avoid internal current leakage, the following bits must be set to 0: DSS.DSS_CONTROL[5] DAC_POWERDN_BGZ DSS.VENC_OUTPUT_CONTROL[2:0] PRCM.CM_FCLKEN_DSS[2] EN_TV CONTROL.CONTROL_DEVCONF[18] TVOUTBYPASS

= General Recommendations =