AM18x To AM335x Hardware Migration Guide

=Introduction= This article documents the differences between the TI AM18x ARM-9 based processor and the TI AM335x Cortex-A8 based processor. Note AM18x is the ARM-only version of this processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.


 * AM18x
 * AM335x

= Software Migration Guide =

For more information on software migration, please see:

TBD

= Basic Feature comparison =

The figures and table below show a comparison of the basic features of the AM18x and AM335x devices. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.



= Hardware Migration =

ARM Processor
AM18x is based on an ARM 9 processor, while AM335x is based on an ARM Cortex A8. The table below shows a comparison between these two devices.

Co-processor
AM18x does not contain a co-processor.

The Neon co-processor is supported on AM335x.

Wake-up Controller
AM18x does not contain a dedicated wake-up controller.

AM335x integrates an ARM Cortex M3 core that manages entry and exit of various stand-by and deep-sleep modes.

Graphics Engine
AM335x supports a SGX530 3D Graphics Engine, with maximum frequency of 200 MHz.

AM18x does not contain a graphics engine.

Programmable Real-Time Unit SubSystem (PRUSS)
The PRUSS supported on AM335x is an enhanced version of that on AM18x. In both devices, the PRUSS integrate two independent 32-bit Load/Store RISC processors, or Programmable Real-time Units (PRUs). The PRU cores run at half the CPU frequency on AM18x and at 200 MHz on AM335x.

Enhancements on AM335x include:
 * Additional data memory (8 KB compared to 512 B) and instruction memory (8 KB compared to 4 KB) with SED
 * 12 KB Shared RAM with SED
 * Enhanced GPIO, adding serial, parallel, and MII capture of the PRU input/output pins
 * Scratch pad shared by the PRU cores
 * Multiplier with optional accumulation (MAC)
 * Internal peripheral modules (UART, eCAP, MII_RT, MDIO, and IEP)

The constant table and PRUSS INTC system events are also updated on AM335x.

On-Chip Memory
AM18x has 128KB RAM.

AM335x has 64KB RAM.

External Memory Interfaces
AM18x supports two controllers (EMIFA and DDR2/mDDR memory controller) for interfacing with external memories.

The EMIFA is used to interface with asynchronous and SDRAM external memories. Up to 5 CS signals are supported. The controller supports the following asynchronous devices:
 * NOR Flash (8-/16-bit-wide data),
 * NAND Flash (8-/16-bit-wide data) with 4-bit ECC,
 * 16-bit SDRAM with 128 MB address space

The DDR2/mDDR memory controller is used to interface with DDR2 SDRAM devices and mobile DDR (mDDR) SDRAM devices. (Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported.) The controller supports a 16-bit wide data path and one CS signal. Only little endian mode is supported. The following CAS latencies and internal banks are supported:


 * CAS latencies:
 * DDR2: 2, 3, 4, and 5
 * mDDR: 2 and 3
 * Internal banks:
 * DDR2: 1, 2, 4, and 8
 * mDDR: 1, 2, and 4

AM335x supports a memory subsystem that includes the GPMC and EMIF for interfacing with external memories.

The GPMC provides an 8/16-bit asynchronous interface for:
 * Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
 * Asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash devices
 * NAND Flash
 * Pseudo-SRAM devices

The controller supports up to 7 CS signals and uses Hamming code to support 1-bit ECC and an integrated Error Locator Module (ELM) to support 4-bit, 8-bit, or 16-bit ECC based on BCH algorithms.

The EMIF provides a 16-bit interface to mDDR (LPDDR1), DDR2, and DDR3 memories. The controller supports a 16-bit wide data path and one CS signal. Both big and little endian modes are supported. The following CAS latencies and internal banks are supported:


 * CAS latencies:
 * DDR2 => 3, 4, 5, 6, and 7
 * DDR3 => 5, 6, 7, 8, 9, 10, and 11
 * mDDR => 2, 3, and 4
 * Internal banks:
 * DDR2 => 1, 2, 4, and 8
 * DDR3 => 1, 2, 4, and 8
 * mDDR => 1, 2, and 4

Voltage Rails
The following table compares the power supplies for AM18x and AM335x:

* Note: These voltage rails are not available in the 13x13 package.

Power modes
The following table compares the power modes for AM18x and AM335x:

* ''Note, the Power and Sleep Controller (PSC) is used to enable and disable any peripheral. This prevents consumption of any unnecessary power.''

Internal Clocks
The following table compares the clock inputs for AM18x and AM335x:

On AM18x, the reference clock for the PLL has the option to be sourced from the on-chip oscillator or an external clock on the OSCIN pin. The AM335x has the option to obtain the 32KHz clock from the high frequency 20MHz clock using an internal RTCDIVDER. If this is used, an external 32KHz clock source is not necessary. The 32KHz provides a clock for the following modules:


 * RTC
 * GPIO0/1/2/3
 * TIMER1/2/3/4/5/6/7
 * ARM
 * SYNCTIMER

PLLs
AM18x has the following phase-locked loop controllers (PLLCs), driven by the reference clock for PLLs:


 * PLL0 - for ARM RAM/ROM, Shared RAM, UART0, EDMA, SPI0, MMC/SDs, VPIF, LCDC, SATA, uPP, DDR2/mDDR bus ports, USB2.0, HPI, PRU, EMIFA, SYSCFG, GPIO, PLLCs, PSCs, I2C1, EMAC/MDIO, USB1.1, ARM INTC, ARM, EMAC RMII clock, I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP serial clock, Observation clock
 * PLL1 - for mDDR/DDR2 PHY

AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):


 * Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRUSS IEP, Debugss
 * Peripheral (Per) PLL - for USB PHY, PRUSS UART, MMC/SD, SPI, I2C, UART
 * MPU PLL - for MPU Subsystem (includes Cortex A-8)
 * Display PLL - for LCD Pixel Clock
 * DDR PLL - for EMIF

Power Management Feature Comparison

 * * On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.

Bootmodes
The available bootmodes for AM18x and AM335x are shown in the table below.

LCD
The AM335x LCD controller is an upgraded version from the controller in AM18x. The enhancements include:


 * Higher resolution support (up to WXGA) vs XGA on AM18x
 * 24bit output (8bpp) vs 16bit output on AM18x
 * Increased horizontal blanking fields HSW/HFP/HBP to 10 bits vs 8bits on AM18x

VPIF
The VPIF module does not exist on AM335x.

MMC/SD
The AM18x and AM335x devices support different versions of industry standards (shown below). The FIFO sizes are also different on each device: AM335x supports a 1024-byte FIFO, and AM18x only supports a 512-bit FIFO.

* Note the supported data width is subject to pinmux constraints.

USB
AM18x supports one USB 1.1 OHCI (Host) With Integrated PHY (USB1) and one USB 2.0 OTG Port With Integrated PHY (USB0). The USB 2.0 OTG peripheral supports 4KB endpoint FIFO RAM.

AM335x supports two USB 2.0 High Speed OTG Ports with integrated PHY. This USB peripheral supports 32KB endpoint FIFO RAM.

I2C
Both AM18x and AM335x support 3 I2C ports.

The AM18x I2C generates 7 interrupts to the CPU and contains a I2C data transmit register (ICDXR) and I2C receive shift register (ICRSR) each holding up to 8 data bits.

The AM335x I2C generates 12 interrupts to the CPU. The I2C's built-in configurable FIFOs (32 bytes size) are used for buffered read or write.

UART
AM18x has 3 UART ports, all supporting modem control signals. None of the UART ports support IrDA. The AM18x UARTs are functionality compatible with the TL16C550 UART. AM18x UARTs support 16-byte transmit and receive FIFOs.

AM335x has 6 UART ports, all supporting IrDA / flow control and only 1 instance supporting full modem control. AM335x allows 1 instance of UART rx/ tx lines to be muxed with USB DP/ DM lines. The UARTs are functionality compatible with the TL16C750 (and TL16C550) UART. AM335x UARTs support 64-byte transmit and receive FIFOs.

MCBSP/McASP
The McASP ports on AM335x and AM18x are functionally identical. Note the McASP is a superset of the McBSP. It is suggested to use the McASP ports for McBSP functionality.

AM18x has 2 McBSP ports and 1 McASP ports. McASP0 supports up to 16 McASP serializers. AM335x has no McBSP ports and 2 McASP ports. McASP0/1 support up to 4 McASP serializers.

SPI
Both AM18x and AM335x support two (2) SPI ports. The AM18x SPI supports 6 CS and 2-16 bit word length. The AM335x SPI supports 2 CS and 4-32 bit word length.

Ethernet
AM18x supports one Ethernet MAC with a maximum data rate of 100 Mbps. The AM18x MAC interfaces include MII/RMII and MDIO.

AM335x supports two Gigabit Ethernet MACs with an integrated switch, with reset isolation, and supporting 1588 precision time stamping. The AM335x MAC interfaces include MII/RMII/RGMII and MDIO.

eCAP/ eHRPWM/ eQEP
The eCAP and eHRPWM modules supported on AM18x and AM335x are identical. The eQEP module is a new interface on AM335x.

AM18x supports the eCAP and eHRPWM peripherals as separate modules. AM335x integrates eCAP, eHRPWM, and eQEP into a single subsystem.

HPI
The HPI module does not exist on AM335x. It is suggested to use GPMC to achieve 16-bit parallel port functionality.

uPP
The uPP module does not exist on AM335x.

SATA controller
The SATA controller does not exist on AM335x.

GPTimer
AM18x supports three (3) one 64-bit or two 32-bit GPTimers. All GPTimers are pinned out.

AM335x supports seven (7) 32-bit GPTimers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 4 GPTimers (DMTIMER4 - DMTIMER7) are pinned out.

WDTimer
AM18x supports 1 WDTimer that can be configured as one 64-bit or two 32-bit WDTimers.

AM335x supports 1 32-bit WDTimer.

RTC
AM18x and AM335x both support 1 RTC.

The AM335x RTC adds a keep alive LDO to power the RTC core logic and supports wake up events to the Cortex M3 for wake up.

GPIOs
AM18x supports 9 banks of GPIO signals. Each bank supports 16 GPIOs and one interrupt.

AM335x supports 4 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts.

New Interfaces in AM335x
The following are new interfaces in the AM335x device that do not exist in AM18x. Any details about these interfaces can be found in the Technical Reference Manual for AM335x.


 * Mailbox
 * eQEP
 * TS/ADC
 * CAN - Controller Area Network Interface

Pin and package
The AM18x and the AM335x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM18x and the AM335x devices.