AM37x/DM37x Schematic Checklist

'''  Content is no longer maintained and is being kept for reference only! ''' = Introduction =

This article applies to the following devices:
 * AM3715
 * AM3703
 * DM3730
 * DM3725

Here are some links to schematics you can refer to:


 * Beagleboard: http://beagleboard.org/resources
 * AM37x EVM: http://www.mistralsolutions.com/assets/downloads/AM37x_EVM.php

If migrating a design from OMAP35x, you should review the OMAP35x To AM37x Hardware Migration Guide.

= Recommendations Specific to AM37x/DM37x =

Power

 * If using TPS659xx devices, please refer to the following app notes for more information on schematic and layout recommendations:
 * SWCA073
 * SWCA076
 * SWCU056
 * SWCU055


 * Check decoupling capacitors (refer to the appropriate Data Manual for your device). Recommend 1 capacitor per 2 to 4 balls.
 * VPP : should be left unconnected for production
 * If using TPS6595x PMIC, SYS_OFFMODE should be connected to TPS6595x nSLEEP1
 * If using TPS6595x PMIC, SYS_CLKREQ should be connected to TPS6595x CLKREQ. On OMAP3EVM, there is a pullup on this signal, but for proper low power functionality, this needs to be removed on the EVM, otherwise the 100K internal pull down in the TPS6595x did not adequately pull down this signal.  SYS_CLKREQ is actively driven when the processor is requesting a high frequency clock, otherwise the signal is in high impedance.  SYS_CLKREQ signal polarity is programmable using PRM_POLCTRL register, so ensure your external hardware matches the intended use of this signal.


 * If using TPS65023, refer to the TPS65023 Design-In Wiki
 * If using TPS65073, refer to the TPS65073 Design-In Wiki

Resets

 * Typically, warm reset is used for a push button reset or reset from external circuits. Use a 4.7K pull up, and connect to nRESWARM on TPS659xx if using those PMICs.
 * nSYSRESPWRON is connected directly to nRESPWRON on the TPS659xx devices. Be careful when connecting this to other reset sources (including push buttons).  Generating a POR in this method could cause the TPS659xx devices to cut power because the warm reset sequence has not be programmed into the TPS659xx device, or the SLEEP sequence has not been programmed into the TPS659xx device.  Typically, other reset sources should be connected to the warm reset.

System signals
If you are using POP memory
 * Connect POP_INT0_FT and POP_INT1_FT to GPIOs to indicate POP die events to the processor
 * Connect POP_TQ_TEMP_SENSE_FT to GPIO to monitor temperature of POP DDR
 * Connect POP_RESET_RP_FT to SYS_NRESWARM to reset flash memories in the event of a warm reset.

Pin states

 * Check reset states of pins connected to other devices. Pins may have inadvertent states at or right after reset which may conflict with external devices.  Especially check GPIOs connected to booting sources, so that these will be in the correct state when booting.  Reset information per ball can be found in the Data Manual "Ball Characteristics" table.  Check the columns Ball Reset State, Ball Reset Rel. State, and Reset Rel. Mode.

Clock Signals

 * SYS_CLKREQ is an open source type signal. You do have control of an internal pull up/down depending on the signal polarity, however an external pull up/down is recommended when this signal is used as an output to control an external oscillator or other clock source. An external pull down is recommended if you plan on using SYS_CLKREQ with active high polarity (PRM_POLCTRL.CLKREQ_POL=1). An external pull up is recommended if you plan on using SYS_CLKREQ with active low polarity (PRM_POLCTRL.CLKREQ_POL=0).

Layout Guidelines
These are generic layout guidelines for BGA packaging: BGA PCB Design Guidelines BGA Decoupling Capacitor Guidelines

I2C

 * Pull ups on SDA and SCL. 4.7K can be used.  When implementing high speed I2C, lower values (470ohm) should be used.
 * If using a TPS659xx device:
 * I2C1 should be connected to TPS659xx I2C.CNTL control interface
 * I2C4 must be connected to TPS659xx I2C.SR smart reflex interface

GPIO
GPIO120-129 are 1.8V or 3.0V. These are the only GPIOs that are 3.0V capable. All others are 1.8V. Also check Additional Configuration for GPIO120-129 on OMAP35x (applicable for AM/DM37x) for further information.

The following GPIOs are input only: GPIO99,100,105,106,107,108,112,113,114,115

Different GPIOs are used to generate wakeup events based on which power domains are active: Ensure that if you intend to use a GPIO as a wakeup event, you connect it to the appropriate GPIO signal.
 * When only the WAKEUP power domain is active (ie, OFF mode), GPIO_1, 9, 10, 11, 30, and 31 can be used to generate a wakeup event.
 * For the rest of the GPIOs in the GPIO1 module (GPIO_0-31, not include the ones above), they can only generate wakeup events if the CORE power domain is active.
 * For GPIOs in modules GPIO2-6 (ie, GPIO_32-191), they can only generate wakeup events if the PER power domain is active.

MMC interface

 * MMC_CLK : no pull ups needed
 * MMC_CMD, MMC_DATx : 10K pull ups needed on each signal, unless using it in SDIO mode (eg., connected to a WLAN device) . Be sure to pull up to MMC voltage (on MMC1, that can be 1.8V or 3.0V)
 * MMC1_CLK, MMC2_CLK and MMC3_CLK, series resistor is needed, place as close to the processor as possible. Recommended value is 33ohm, but will need to be adjusted based on trace length to the MMC peripheral.
 * When using MMC1, VDDS_MMC1 supplies power for MMC1_DAT(0-3), and VDDS_X supplies power for MMC1_DAT(4:7). So if using 8-bit mode, both VDDS_MMC1 and VDDS_X need to be connected to the same power source.  If using 1-bit or 4-bit mode, power to VDDS_MMC1 only needs to be applied.  Pull VDDS_X low with 5-10K resistor if not using MMC1_DAT(4-7).  In this scenario, you can use MMC1_DAT(4-7) for GPIOs, if needed.  These can be supplied from a different power source on VDDS_X, depending on the voltage level you need for the GPIO (1.8V or 3.0V).
 * If using MMC1_WP (write protect) and MMC1_CD (card detect) signals, they would typically be pulled up to 1.8V before connecting to the processor GPIO or TPS659xx GPIO. MMC1_CD can be used as a power saving feature to detect insertion of the card even when you have shut off the power via VDDS_MMC1 (or VDDS_X).  Connecting it to TPS659xx device will allow it to turn on/off voltage upon insertion/removal of the card.  Similarly, connecting MMC1_CD to the processor will allow for an interrupt to enable an external power source to turn on/off upon insertion/removal of the card.
 * MMC2 and MMC3 interfaces are 1.8V only. You can connect MMC2 to 3.3V devices using an external transceiver (see block diagram in TRM).  The transceiver must include a clock output that will connect to MMC2_CLKIN.  MMC3 should only be used with 1.8V devices.  It should not be connected through a transceiver.
 * Also refer to SD-MMC Usage Notes wiki for more information

TV OUT interface
Refer to the [[Media:TV_out_application_note.pdf|TV out Application note]].

DSS

 * Refer to the Display Subsystem wiki for guidance on connecting the DSS.
 * Add 10ohm series resistors to all data lines, HSYNC, VSYNC, ACBIAS, PCLK
 * The DSS signal connection changes depending your PCLK.

Backward compatibility is maintained if your pixel clock on DSS interface is < = 60 MHz. But if your pixel clock is higher, 60 < PCLK < = 75 MHz, you would need to use the High Speed Mode pinmux scheme. For all new AM/DM37x designs, High Speed Mode pinmux scheme should be used.

GPMC

 * check to make sure any pullups for WAIT signals are 1.8V
 * if used, ensure GPMC_CLK has 33ohm series resistor placed close to AM/DM37x

McBSP

 * Some McBSPs have different sized internal FIFOs. McBSP2 has 5K FIFO (others have only 512 bytes).
 * McBSP2 and McBSP3 have sidetone capabilities.
 * Place 33ohm series resistor close to AM/DM37x on all McBSP clock signals.

USB OTG

 * for OTG operation, USB VBUS decoupling capacitance should be 1-6.5uF
 * for device operation, USB VBUS decoupling capacitance should be < 10uF.
 * for host operation, USB VBUS decoupling capacitance should be > 120uF
 * ensure the VBUS decoupling capaciance is connected close to USB connector.
 * ID signals should not be pulled down with a pull down resistor. If defaulting to an A-device, ground the ID signal on the USB PHY.

USB Host ports (HSUSB1 - HSUSB3)

 * HSUSB3 will only support FS/LS USB PHYs.
 * Review the AM37x Errata for issues concerning USB Host ports.
 * For USB Host ports (USB1 and USB2), we recommend using TI's TUSB1210 USB PHY. This PHY supports input clocking mode (ie, the PHY is in slave mode and the processor sources the 60MHz ULPI clock). This device has recently been released and has been proven to work with AM/DM37x devices.
 * Some layout recommendations for the TUSB1210
 * Ensure trace length matching between all of the data signals and CLK and STP. Skew mismatch should be less than 10-20%
 * Trace length of CLK is important. It should never be longer than the data signals.  Layout the TUSB1210 so that the CLK pin faces the AM/DM37x device, so you can get the CLK the same or shorter (within 10-20%) than the data signals.
 * Ideally, CLK and STP should be a close to the same length as possible.
 * If using an SMSC3320, you must supply a dedicated low noise power source for 1.8V. This PHY is highly susceptible to noise on this rail and careful consideration must be used when designing with this part.  Ideal reference design layout with this device can be found at the Beagle Board website.
 * The TUSB1210 and SMSC3320 are pin-for-pin compatible, with some minor modifications. If you want to design your board to accomodate both, please see the [[Media:OMAP3EVM_REVG_mods_to_use_TUSB1210.zip|following schematic]], which details the changes that need to be made to the OMAP3EVM to change from the SMSC332x to the TUSB1210.

mDDR

 * Ensure that you follow the recommended layout guidelines and series termination values in section 6.4.2 of the Data Manual

McSPI

 * place 33ohm series resistor close to AM/DM37x on all MCSPI clock signals.

What to do with unused Power signals

 * VDDA_DAC: if signals powered by VDDA_VDAC are not used, pull low with 5-10K resistor to ground.


 * VDDS_MMC1/VDDS_X: if MMC1/MMC1a is not used, pull low with 5-10K resistor to ground.  See MMC section above for more details


 * VDDS_SDI: always connect this to 1.8V, even if SDI is not used.  This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals.  VDDS should should always be powered.


 * VDDS_CSI2: if signals powered by VDDS_CSI2 are not used, pull low with 5-10K resistor to ground.  This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals.  VDDS should should always be powered.


 * VDDS_CSIB: always connect this to 1.8V, even if CSIB is not used.  This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals.  VDDS should should always be powered.


 * VDDS_DSI: always connect this to 1.8V, even if DSI is not used.  This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals.  VDDS should should always be powered.


 * VDDS_X: if signals powered by VDDS_X are not used, pull low with 5-10K resistor to ground.  This signal is called VDDS_X in the latest datasheets.  See above for recommendations.

TV Output
When the TV output is not required then the following configuration should be implemented in order to reduce the power consumption to its minimum value.

The analog pins tv_vref, vssa_dac, VDDA_DAC, tv_out1/2 and tv_vfb1/2 should be grounded. (Signal names appear as CVIDEO1_OUT, CVIDEO1_VFB, CVIDEO2_OUT, CVIDEO2_VFB, CVIDEO1_RSET in TRM SPRUGN4M)

To avoid internal current leakage, the following bits must be set to 0: DSS.DSS_CONTROL[5] DAC_POWERDN_BGZ DSS.VENC_OUTPUT_CONTROL[2:0] PRCM.CM_FCLKEN_DSS[2] EN_TV CONTROL.CONTROL_DEVCONF[18] TVOUTBYPASS

= General Recommendations =