AM387x / C6A814x PCB Layout guide

= Introduction =

This article applies to the following devices:

DM814x C6A814x AM387x DM8127

== This is a PRELIMINARY AM387x/C6A814x CYE package Layout Guide. These files are not finished, but do show a valid BGA escape for the signals. The power section is not done, but the user should be able to figure this out on their own. We plan do write an official guide, but this is to help users until that guide is done ==

Here is the .pdf file of the signal escape. The DRC errors at the bottom are because the DDR line lengths are too short (since they're not finished). The signal escape is complete, but the power and ground layers are not yet done. I just started the bypass cap placement and routing.

Here is the Allegro file, Version 16.2. Unfortunately I'm not sure how to get this in pre-16 versions. The same comments above apply to this file. Hopefully this helps.

The PCB rules that were followed for this layout are:

20 mil vias/10 mil finished hole size

4 mil traces

4 mil clearances

All balls routed in 2 signal layers