AM335x Schematic Checklist

= Introduction =

This article applies to the following devices:
 * AM3352
 * AM3354
 * AM3356
 * AM3357
 * AM3358
 * AM3359

Here are some links to some TI hardware designs based on AM335x:


 * Beaglebone: http://beagleboard.org/bone
 * AM335x GP EVM: http://www.ti.com/tool/tmdxevm3358
 * AM335x Starter Kit: http://www.ti.com/tool/tmdssk3358
 * AM335x IA EVM: http://www.ti.com/tool/tmdxidk3359
 * AM335x Industrial Communication Engine [ICE]: http://www.ti.com/tool/tmdxice3359

If migrating from a previous TI processor, you can use the following migration guides as a start:
 * http://processors.wiki.ti.com/index.php/AM35x_To_AM335x_Hardware_Migration_Guide
 * http://processors.wiki.ti.com/index.php/AM37x_To_AM335x_Hardware_Migration_Guide
 * http://processors.wiki.ti.com/index.php/AM387x_To_AM335x_Hardware_Migration_Guide

'''Don't forget to check the AM335x errata when designing a board (see the product folder on ti.com). This will have important information on silicon issues which may alter your board design.'''

Other useful links:
 * AM335x Layout Guidelines

= Recommendations Specific to AM335x =

Unused Signals
Signals on interfaces that are unused can typically be left as no connect. Many of the IOs have a Pad Control Register (see Chapter 9 of the TRM for more details) which gives control over the input capabilities of the I/O (RXACTIVE field in each conf_ _ register). Software should disable the I/Os which are no connects (ie, RXACTIVE=0) as soon as possible in initialization. This RXACTIVE field defaults to "input active" for most signals, which means there is a potential for some leakage during powerup of the chip if the input floats to a mid-supply level before the software can initialize the I/O. This should only be a concern if you are attempting to power up the design with a minimum power consumption. Most designs should be able to tolerate this small amount of leakage in each floating I/O until the software has a change to disable it. After disabling the I/O, no leakage will occur.

If ADC is not used...

 * Connect all TSC_ADC terminals (VREFP, VREFN, AIN[7:0], VDDA_ADC, and VSSA_ADC) to same ground as all VSS terminals.

If USB0 or USB1 is not used...

 * Connect the respective VDDA1P8V_USB terminal to any 1.8-V power supply and respective VDDA3P3V_USB terminal to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
 * The OTG_PWRDN and CM_PWRDN bits in the respective USB_CTRL register can be used to power down the unused USB PHY to minimize power supply leakage current. These bits default to the powered-up state after the AM335x device has been reset. The USB PHY can be powered down by setting both of these bits to "1".
 * The respective VBUS, ID, DP, and DM terminals may be connected to ground or left floating.
 * The respective CE terminal should be left floating.

If RTC internal oscillator is not used...

 * This can be the case when:
 * A 1.8 volt LVCMOS clock source is used rather than a crystal circuit
 * Connect the clock source to the RTC_XTALIN terminal, leave the RTC_XTALOUT terminal open-circuit, and connect VSS_RTC to VSS if using the ZCZ package option
 * The AM335x RTC is not used
 * Leave the RTC_XTALIN and RTC_XTALOUT terminals open-circuit, and connect VSS_RTC to VSS if using the ZCZ package option

Pinmux
All pinmux settings must be verified using the TI Pinmux Tool to ensure valid IOSets have been used. The tool can be downloaded from http://www.ti.com/tool/pinmuxtool

Pullups

 * ensure all pullups connected to AM335x are pulled up to the correct I/O voltage to avoid any leakage between the I/O rails of AM335x. Each terminal has an associated voltage used to power its I/O cell. This can be found in the AM335x datasheet, in the Ball Characteristics table under the "ZCE Power/ ZCZ Power" column.
 * For example, if you want to pull up terminal SPI0_CS0 in any mux mode (gpio0_5, i2c1_scl, etc.), pull up the signal to VDDSHV6.

General Debug

 * output clocks CLKOUT1 and CLKOUT2 are present on terminals XDMA_EVENT_INTR0 and XDMA_EVENT_INTR1. If these are not used in your design, it is good to have test points on these signals to be able to monitor internal clocks.

Warm Reset

 * be sure to check the TRM for uses for warm reset. The warm reset signal should be used as an input (for example, connected to a push button) or output (to reset external devices during a POR).  It cannot be used for both because of an errata with the clocking of the debounce circuitry.

Peripheral Clocking
Several peripheral clocks are required to have RXACTIVE bit set as input because they are used to retime read data returning to the device. We also recommend a series resistor located as close to the device as possible to reduce reflections on the clock. For the following peripherals, the associated signals should have a series resistor (33ohm) in line as close to the processor as possible when used in master mode (ie, AM335x drives the clock) GPMC - GPMC_CLK MMC - MMC_CLK I2C - I2C_CLK SPI - SPI_CLK McASP (all clocks and frame syncs)

Low Power considerations
If you are designing for low power, here are some tips to help you optimize your design for low power
 * The TPS65217C and TPS65217D do not support RTC-only mode. TPS65218 does.
 * On early prototype boards, it is recommended to include small shunt resistors in the voltage rail paths of each of the following rails of AM335x: VDD_MPU, VDD_CORE, VDDS, VDDSHV1-6, VDDS_DDR. This will help you measure the power consumption of each rail and potential pinpoint high power consumption during development.  You may also want to add these shunt resistors for other devices power supplies to be able to measure power for key devices.  The AM335x EVMs have examples of these shunt resistors.
 * For production, these shunt resistors should be removed from the design (i.e. turned into a continuous plane), especially for designs using Smart Reflex.


 * Only GPIO0 signals are capable of wakeup signaling (to wakeup from DeepSleep or RTC modes). Connect wakeup sources only to these GPIOs (GPIO0_0 to GPIO0_31).
 * For your main clock (e.g. 24 MHz, etc.) you can use either a crystal or a LVCMOS square wave clock. There is a power benefit to using a crystal because there is hardware inside the chip that can shutoff the crystal entirely during DeepSleep0 (DS0).  When using a square wave clock there is unfortunately no mechanism for automatically turning the clock off and on, which results in additional current consumption.
 * If your design uses VTT you should use a pin from GPIO bank 0 to control the regulator. This will enable the regulator to be switched off during DS0.
 * The Cortex M3 uses I2C0 for communication with the Power Management IC (PMIC) for purposes of reducing the voltage during DS0.

Clocking

 * If you do not need RTC-only mode and the RTC timer feature, you do not need to include a 32KHz crystal. The 32KHz reference can come from the high frequency clock. Leave the RTC_XTALIN/RTC_XTALOUT pins as NC.
 * Per Advisory 1.0.30, VSS_OSC and VSS_RTC should be connected to system ground.
 * It is preferable to always have bias and dampening resistors that can help tune the crystal later. See section 4.2.2 of the datasheet for more details.

General DDR guidelines
These guidelines are applicable for all DDR designs:


 * It is very important to follow the DDR routing guidelines for your DDR type in the AM335x datasheet. These guidelines are very important to ensure a proper DDR design.
 * Ensure resistor for DDR_VTP is a high precision resistor as specified in the datasheet. A 49.9ohm 1% resistor is less expensive than a 50ohm 2% resistor and can be used for the DDR_VTP pin for cost sensitive designs.
 * When using a resistor divider for DDR_VREF, ensure resistors are high precision resistors as specified in the datasheet
 * allow for adequate decoupling capacitors on the DDR power rails both at the AM335x as well as the DDR SDRAM device(s)

DDR2

 * DDR_VREF can be derived using a resistor divider with decoupling to both DDR supply and ground. Follow the recommendations as documented in the DDR2 Routing Guidelines of the data sheet.

DDR3

 * For point-to-point DDR3 topologies (e.g. single x16 DDR3 IC), VTT termination is not needed. Designs using two x8 DDR3 IC’s may wish to consider using a termination regulator such as the TPS51200 for the address/control signals.
 * If using VTT termination...
 * Do not use VTT termination for DDR_RESET. It should be connected directly from the AM335x to DDR.
 * If VTT regulator is disabled during low power modes (e.g. by programming EN=0 using the TPS51200), DDR_CKE should not be connected to termination resistors. The active discharge capability of the regulator can cause a brief dip on this signal which can be problematic.  This would likely be true of any VTT regulator with active discharge capability.
 * Termination for clock signals is VDDS_DDR (along with an AC coupling capacitor), whereas all other signals need to use VTT for the termination voltage. Check the datasheet for details.
 * If not using VTT termination, VREF should be obtained using a resistor divider (10Kohm 1%) with capacitive decoupling to ground, and should be used as a reference for both CA and DQ pins on the memory, as well as the VREF signal on AM335x. Be sure to use high precision (1%) resistors as specified in the datasheet.  When not using VTT, be especially sure to follow the routing guidelines in the datasheet.

MMC

 * include a 22ohm series resistor on MMCx_CLK (as close to the processor as possible). This signal is used as an input on read transactions and the resistor will eliminate possible signal reflections on the signal which can cause false clock transitions.
 * this also requires you to set RXACTIVE=1 in the pinmux configuration for the MMC_CLK signal.
 * When connecting a device (card or eMMC), include 10k pullups on RST#, CMD, and all DAT signals.

I2C

 * pullups on both I2C signals (I2C_DATA and I2C_CLK) should be 4.7K. Ensure the pullups connect to the correct I/O voltage rail.  See note on Pullups above.
 * if you are planning to use TI's software (SDK or Starterware), be sure to connect I2C0 to the PMIC, as this is the port used for PMIC control.

LCD

 * Please be sure to consult the silicon errata for the proper pinout of the LCD interface. There is a usage note titled, "LCD: Color Assignments of LCD_DATA Terminals".
 * Note that the EVM "fixes" the pin mapping through a CPLD on the daughterboard, so be extra careful to get the proper mapping!
 * A good example of a 24-bit hookup comes from the Starter Kit:
 * [[Image:Starter-kit-24bit-lcd.png]]


 * A good example of a 16-bit hookup comes from the BeagleBone Black. In this case they were preserving the other LCD pins for use by capes:
 * [[Image:Bbb-16bit-lcd.png]]


 * Notice that Red and Blue swap positions depending on whether you're outputting in 16-bit mode vs 24-bit mode (i.e. that's the errata...).

Power

 * AM335x Power Solution




 * Check the product pages on each device for application notes specific for connecting the PMIC to AM335x.  Also check the product data sheet for specific part numbers to be used for the AM335x


 * Powering the AM335x With the TPS65217x (SLVU551)
 * Powering the AM335x With the TPS650250 (slvu731)
 * TPS65910x User's Guide for AM335x Processors (SWCU093)
 * TPS65910x Schematic Checklist (SWCA139)


 * ensure current capabilities of DCDC switchers and LDOs meet the maximum demand of all devices that are attached. You can find the maximum current draw of all AM335x I/O rails in the datasheet.  If these rails from the PMIC also power other devices, the maximum current draw of these devices need to be taken into consideration as well.
 * ensure I2C0 is used for communication to PMIC. All TI software distributions (linux SDK, Starterware, etc.) assumes the use of this interface with the PMIC.

Touchscreen

 * recommend adding 0ohm resistor to VDDA_ADC in case you need to add a filter for noise on the ADC.
 * Check out the sampling voltage must not exceed the voltage of reference. Otherwise, it will affect the whole TSC_ADC system. (Ex: if you add pull up to 3.0V at the last four channel, this will lead to the abnormal work of the whole system, including the first four).

USB

 * The AM335x USB0_ID and USB1_ID terminals should never be connected to any external voltage source. These terminals should be open-circuit when the respective USB port is configured to operate in USB peripheral mode, or should be connected to ground when the respective USB port is configured to operate in USB host mode.
 * USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points.
 * Typical connections for a USB peripheral:
 * USBx_DP and USBx_DM are connected directly to the USB connector
 * USBx_CE can be used if supporting charging. This generally would be connected to the enable of a charging source for the battery.
 * USBx_ID can be left unconnected
 * USBx_DRVVBUS is not used and can be left unconnected
 * USBx_VBUS should be connected directly to the VBUS pin on the USB connector
 * Typical connections for a USB host:
 * USBx_DP and USBx_DM are connected directly to the USB connector
 * USBx_CE is typically not used and can be left unconnected
 * USDx_ID should be grounded
 * USBx_DRVVBUS should be connected to the enable of the 5V VBUS power source.
 * USBx_VBUS should be connected to the output of the 5V VBUS power source
 * Typical connections for a USB host with USB hub:
 * USBx_DP and USBx_DM are connected directly to the USB hub upstream port. The hub then distributes these signals to the downstream ports as needed.
 * USBx_CE is typically not used and can be left unconnected
 * USDx_ID should be grounded to enable host mode.
 * USBx_DRVVBUS should be connected to the enable of the 5V VBUS power source.
 * USBx_VBUS should be connected to the output of the 5V VBUS power source. It is also connected to the VBUS detect on the hub, which then allows the hub to selectively enable/disable typically through a power switch to each downstream port.

External Interrupt (EXTINTn)

 * This signal is active high for PG1.0 and active low for PG2.x. Boards designed to support all silicon revisions may want contain population options for both in case you move between different revisions of the AM335x during development.  New designs are expected to use only PG2.1.
 * This signal connects directly to the Cortex A8 interrupt controller, which as a result makes this a level sensitive pin. It is recommended to consider using a GPIO signal instead of EXTINTn.  The GPIO pins offer more flexibility with respect to polarity as well as the ability to be edge triggered.

Ethernet

 * While no series resistors are required for MII/RMII/RGMII, it is prudent include zero-Ohm stuff options for the TX and RX lines. Ideally, these option resistors should be as small as possible (0402 or smaller recommended) and should be placed as close to the transmitter as possible.

RTC
The following table describes what to do with each pin related to RTC functionality. Three use case scenarios are provided:


 * RTC-only mode: If you will be using the low power RTC-only mode. This use case allows low power operation of the AM335x by allowing only the RTC power supply to be ON while all the remaining supplies are OFF.
 * RTC timer functionality but no RTC-only mode: If you will be using the RTC feature but do not need RTC-only mode. This use case allows you to use the Real Time clocking features (eg, keeping time), but you do not need to support the low power RTC-only mode.
 * RTC feature disabled: If you will never use the RTC features. In this use case, the RTC functions are fully disabled.

 Note 


 * 1) The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
 * 2) If the internal RTC LDO is disabled,CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
 * 3) RTC_PWRONRSTn should be asserted for at least 1ms for internal RTC LDO output voltage stabilized when internal RTC LDO is enabled.
 * 4) VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE.
 * 5) RTC_PWRONRSTn high level must be 1.8V.  It cannot be 3.3V.  If tied together with PWRONRSTn, both reset inputs high level must be 1.8V
 * 6) If using an external LVCMOS input for the 32 kHz clock it must be 1.8V amplitude since this pin is related to VDDS_RTC.

= General Recommendations =