AM3517/05 Memory Subsystem

'''  Content is no longer maintained and is being kept for reference only! '''

= Memory Subsystem =

The Memory Subsystem in the AM3517/05 devices consists of the internal SRAM and two dedicated memory controllers (GPMC and SDRC)



SDRAM Controller (SDRC)
The SDRC provides an interface to LPDDR1 and DDR2 Memory devices operating at 166MHz (333DDR). For further informationa please visit the AM3517/05 SDRC subsystem wiki page

General Purpose Memory Controller (GPMC)
The GPMC is a 16-bit external memory controller. The GPMC data access engine provides a flexible programming model for communication with all standard memories:


 * Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
 * Asynchronous, synchronous, and page mode (only available in non-muxed mode) burst NOR flash devices
 * NAND flash
 * Pseudo-SRAM devices

For more inforamtion on the GPMC, please visit the AM3517/05 GPMC subsystem wiki page

SRAM
Functional Description