AM57xx PCB Escape Routing

= AM57xx BGA Escape Routing =

Stackup
The PCB Layout designer needs to balance many different requirements when starting a PCB layout. The first is the board stackup. The AM572x family of devices have a 23mm x 23mm package which has a 0.80mm pitch ball array of 28x28. To minimize cost, this ball grid is nearly a solid array. Due to the number of rows of signal balls around the periphery, designs will need to have 4 routing layers not counting the top and bottom layers which can also contain some signal routes. Also, due to the number of power supply rails, there will need to be 2 layers dedicated for power planes. Ground planes will need to be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. Therefore, designs that route out all of the signal balls will need a 12-layer stackup similar to the following:


 * Note that tracks are assumed to be perpendicular. Broadside coupling must be minimized to prevent crosstalk problems.  Otherwise additional Ground planes must be inserted between the signal routing layers.

A 12-layer stack-up like the one discussed above will be needed for relatively dense PCBs. Alternately, the layer count can be reduced assuming one or more of the following exist:
 * The PCB is not crowded around the AM57xx device. This allows for more routing away from the device on the top and bottom layers which can reduce layer congestion.
 * Many of the signal balls are unused. Many designs will not use all of the interfaces resulting in unused signal balls.  This also reduces routing congestion.
 * The PCB layout team has time to carefully place the routes. Note that this can be very time consuming.

It is not acceptable to violate routing rules simply to save money on reduced PCB layers or due to limited routing time. All requirements must still be met. Also, creative routing will increase design validation time - both in simulation and bench testing. This can be minimized if the layout is similar to one of the TYI EVM designs.

The AM572 IDK EVM is implemented in a 12-layer stack-up similar to the one described above. This design has nearly every signal ball routed to circuitry or a connector. This drives the requirement for the full number of layers. Additionally, this board is designed for optimum signal integrity on the high speed interfaces while limiting the board size. To accomplish this, the design team chose to implement an HDI (High Density Interconnect) board using micro vias on both the top 2 and bottom 2 layers. This provided optimum routing for the SERDES interfaces and the DDR3 routes on layers 3 and 10 as well as the bottom and top layers since there is no via stub. It also allowed layers 4 and 9 to contain DDR3 routes with very little via stub. It is understood that the HDI stack-up adds cost but it resulted in excellent signal integrity and routing was greatly simplified.

Floorplan Component Placement
Optimum trace routing will have routes as short as possible with a minimum of cross-over. This requires careful placement of the components around the AM572x device. The figure below shows the default arrangement of the signal balls as well as the power and ground balls. (It is understood that some of the interfaces can move to other locations due to pin multiplex choices and that there are other interfaces not listed that are exposed through pin multiplex choices.) The PCB layout team will need to analyze the locations of the interfaces used and the associated components and / or connectors.



Critical Interfaces Impact Placement
Placement of the AM572x device and some of the component and / or connectors will also be dictated by some of the highest performance interfaces. Additionally, due to the PCB losses at multi-gigabit rates, there are routing distance limits that may also limit component placement.

Route Critical Interfaces First
As indicated above, critical interfaces will affect component placement options. Then when routing begins, these critical interfaces must be routed first. The design team needs to establish a priority for the different interfaces. Those with higher priority must be completed before implementing those of lower priority. PCB layout teams often waste considerable effort ripping up and re-routing traces for lower priority interfaces when deficiencies are found in the routing of more critical interfaces. Always complete routing for the critical interfaces first.

The table below lists a recommended priority order for interfaces contained on the AM572x family of devices. Individual design requirements may cause this list to change somewhat but this provides a good baseline.

The placement of most of these should appear obvious. The multi-gigabit SERDES interfaces are the most critical due to their data rate and loss concerns. USB3 is at the top since it is very sensitive to PCB losses. The limited length for these routes might affect the PCB placement of the USB3 connector and the AM572x device. If the distance is too great, a USB3 repeater device may need to be added.

The asynchronous and low speed interfaces are at the bottom. This leaves the synchronous and source-synchronous interfaces in the center ordered by data rate. The one surprise may be power distribution. It is often left to last. This then results in poor decoupling performance and / or current starvation and excessive power supply noise due to insufficient copper to carry the power and ground currents. Space for copper and decoupling needs to be allocated before routing the middle and low priority interfaces.

Route SERDES Interfaces First
The previous section highlighted priorities for the PCB routing. The BGA ball map is also arranged to support routing the highest priority interfaces first. You will notice that most of the SERDES interfaces (SATA, PCIe Lane 0 and HDMI) are all located on the outer rows to allow these to route away from the device without requiring vias. See below for the routing of the PCIe Lane 0 and HDMI signals on the AM572 IDK on the top layer.



The multiplexed pins for PCIe Lane 1 / USB3 are not on the outer 2 rows and they will require vias. See below for the routing of these as USB3 on the AM572 IDK on the third layer. The AM572 IDK design is an HDI stackup using micro vias which allows the USB3 traces to be routed on layer 3 without any via stub. The image also shows the USB2 traces for both port 0 and port 1.



Route DDR3 Signals Next
The DDR3 signals need to be routed next. Please refer to the AM572x Datasheet (SPRS915) for detailed recommendations for DDR3 routing. The images below show the BGA breakout for the first DDR3 port only but the same technique must be used for the second DDR3 port.

The DDR3 SDRAM memory devices should be arranged so that the data group balls are closest to the AM572x device. This will allow the data group nets to have the shortest possible routing. The Address, Command and Control signals operate at half the bandwidth of the data so they are expected to be longer.

Data Group Routes
The next 3 images show the data group routing for the first DDR3 port. Please note that the PCB layout designer grouped all 11 nets for each byte group on a single layer. This is not a requirement but it is strongly recommended as this simplifies the signal length and delay matching requirements.

The following image shows Data Group 1 and Data Group 3. They break out on the top layer and then route on layer 3. Note that due to the use of micro vias, there is no via stub on these routes.



The following image shows Data Group 0 and Data Group 2. They break out on the top layer and then route on layer 10. Note that due to the use of micro vias, there is no via stub on these routes.



The following image shows the ECC Data Group. They break out on the top layer and then route on layer 3. Note that due to the use of micro vias, there is no via stub on these routes.



Address, Command, Control and Clock Group Routes
The next 4 images show the Address, Command, Control and Clock (ACCC) group routing for the first DDR3 port. The first image is an overlay showing these routes on layers 1, 3 and 10. The following images than show each later separately.

Overlay of Address, Command, Control and Clock group routing.

Address, Command, Control and Clock group breakout and routing on the top layer.



Address, Command, Control and Clock group routing on layer 3.



Address, Command, Control and Clock group routing on layer 10.



Complete Power Decoupling Next
The middle priority interfaces and the power distribution planes and pours would be routed next after the SERDES and DDR3 interfaces. It is strongly encouraged to complete all SERDES and DDR3 routing before continuing with other interfaces. Note that the power distribution planes and pours and all of the decoupling will need to be placed before PCB simulations are executed for the SERDES and DDR3 routes. The highest speed source-synchronous interfaces like RGMII and QSPI may also require simulation so these may need to be completed at this time as well.

Route Lowest Priority Interfaces Last
Once the length matching and simulations have been completed for the highest priority interfaces and the Power Distribution Network (PDN) analysis has been completed, then the layout can continue with the medium and then the lower priority interfaces.