AM35x VCA PCB layout

'''  Content is no longer maintained and is being kept for reference only! ''' PCB Escape Routing for ZCN Package

Keven Coates / Paul Eaves

May 2010.......................................................................................................

ABSTRACT

The ZCN package is designed with a new technology called Via Channel™ Array (VCA). This technology allows Ball Grid Array (BGA) devices with 0.65mm ball pitch to be easily routed on a Printed Circuit Board (PCB) with two signal and two power layers using a standard via with 20 mil diameter pads and 10 mil finished hole which is cost and time effective. This application report shows how to easily route the entire device by first routing one quadrant and then copying it to the other three quadrants. The Allegro ® layout tool was used to generate this document but other PCB layout tools could be used in a similar way.

1 PCB Layout Technology

1.1 Via Channel Layout Advantages

Via Channel technology is a way of depopulating solder balls on the BGA device in a shape that makes it possible to have the vias concentrated in channels. This channel provides several advantages. First, all of the vias are placed in special areas called via channels so the outside diameter of the via, also known as the annular ring, can be larger than it normally would be if it were placed between the BGA pads. This makes PCB manufacturing less expensive because 20/10 vias (vias with an outside diameter of 20 mils and a finished hole size of 10 mils) can be used to route signals from the 0.65mm BGA. Second, the vias are grouped in a radial pattern instead of a series of concentric rings around the device as in the case with normal PCB routing of BGAs. The radial pattern allows traces to be easily routed out of the inner parts of the device because they are not restricted to the narrow paths in between many rows of vias. This allows reduced PCB layers because of the increased routing efficiency. With the ZCN package, a four layer PCB design is possible for most systems.

Figure 1 shows the resulting ZCN footprint with via channels.

1.2 Example PCB Layout

An example PCB layout is provided to demonstrate how Via Channel technology can be used to route a 0.65mm ball pitch BGA device with two signal and two power layers using standard 20/10 vias. The Texas Instruments (TI) AM3517 applications processor with ZCN package is used in this example. This example can be used as a layout guide for any TI applications processor offered in the ZCN package if they have the same solder ball assignments as the AM3517. This example may also be used as an approximate layout guide for any TI applications processor offered in other Via Channel technology packages by making the appropriate changes that account for differences in solder ball assignments.

We ’ ll begin by breaking this footprint into four quadrants. A quadrant is defined as one of four equal size squares making up the whole. The upper left square defines quadrant 1 and the other quadrants are numbered clockwise 2 - 4.

The center of the footprint is not symmetrical, but the quadrant to quadrant symmetry of the nine outside rows is identical with the exception of two missing solder balls in locations J6 and J24. We will take advantage of this symmetry by routing one quadrant and copying it to the other 3 quadrants.

For clarity, the via channels for the first quadrant will be numbered 1-6, as shown in Figure 1, with 3 being the corner channel.

Via Channel is a trademark of Texas Instruments.

Allegro is a registered trademark of Cadence Design Systems.

All other trademarks are the property of their respective owners.





Figure 1, ZCN Package Footprint With Via Channel Array

(Most pictures shown with printable colors instead of default black background)

The PCB layout constraints used for routing the device described in this document are:


 * 0.3mm BGA pad (as suggested by IPC standards and TI reliability studies)
 * 4 mil (0.1mm) maximum trace size
 * 20 mil (0.50mm) maximum via diameter
 * 10 mil (0.25mm) maximum finished hole diameter

If done correctly, blind, stacked, buried, or micro vias will not be required and only two signal layers will be required to route this device.

As stated earlier, the best approach to limit the number of steps required to route this device is to route quadrant 1 and rotationally copy the routing from quadrant 1 to the other three quadrants.

This document shows how small sections of quadrant 1 can be routed and copied into similar sections of quadrant 1. After all of the quadrant 1 signal pins are routed, quadrant 1 can be copied to the other three quadrants. Therefore, it only requires a few steps to route all signal pins. After all the signal pins are routed, the ground and power shapes can be defined.

Figure 2 shows the routing of the first two signals on the outside rows.



Figure 2

After the first two signals are routed, they are copied to the remaining top two rows of quadrant 1.

This copy is done using the following procedure:

1. Select the copy command.

2. Select the two traces.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Select the pick box "P" in the lower right hand corner of the screen and enter the relative coordinate offset of "0.65 0" and check the "Relative" box.

5. Click the pick button multiple times until the two traces have been copied across the top two rows of quadrant 1.

6. Click on the Close button.

7. Right click and select "Done".

The result of this copy sequence is shown in Figure 3.



Figure 3

Now the two left rows of the left side of quadrant 1 can be routed in a similar way as the top two rows of quadrant 1.

The first step is to route the first two signals on the left side as shown in Figure 4.



Figure 4

After the first two signals on the left side are routed, they are copied to the remaining left two rows of quadrant 1.

This copy is done using the following procedure:

1. Select the copy command.

2. Select the two traces.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Select the pick box "P" in the lower right hand corner of the screen and enter the relative coordinate offset of "0 -0.65" and check the "Relative" box.

5. Click the pick button multiple times until the two traces have been copied down the left two rows of quadrant 1.

6. Click on the Close button.

7. Right click and select "Done".

The result of this copy sequence is shown in Figure 5.



Figure 5

Figure 6 shows how the corner ball on the third row is routed.



Figure 6

This has been a standard BGA routing exercise so far, but now we will begin using the via channels. This is where the routing is significantly different than a normal BGA route. Vias must be placed in via channels, wired to solder pads on the top layer, and routed out on the bottom layer. In Allegro, the easiest way to do this is by placing multiple vias in an unused area outside the package drawing and then sliding the vias to the channels (with no connections) using the "slide" command. Make sure that you have the "Allow DRCs" check box in the option tab unchecked. This ensures that the vias are placed with adequate clearance to other vias and solder pads by only allowing vias to be placed in a position where they will not generate design rule check (DRC) errors.

After multiple vias are placed in an unused area outside the package drawing, "slide" seven of them to channel 5 of quadrant 1 as shown in Figure 7. It is a tight fit, but they will all fit into the channel with adequate clearance (as defined by the PCB constraints previously stated in this document).



Figure 7

We choose to do channel 5 first because later we ’ ll copy and rotate channel 5 around the center of the chip, copying channel 5 into channel 1. Then we can do a simple copy from channel 5 into channel 6, but we won ’ t do this yet since we have traces to add to minimize the work needed on each channel.

After placing seven vias in channel 5, we can begin placing vias in channel 3. We could have done channel 3 first, but it ’ s a bit more challenging than channel 5.

Place the first via in channel 3 as far as possible into the upper corner between pads C3 and B4. Then place the second via as close as possible to the first via and pad C5. The third via is placed as close as possible to pads D2 and E3.

The placement of the first three vias is shown in Figure 8.



Figure 8

Then place eight additional vias in a pattern as shown in Figure 9.



Figure 9

One via needs to be placed in channel 4, then we can begin adding top-side routing.

Figure 10 shows the top-side routing to the vias in channels 3, 4, and 5. There is some flexibility in the routing of these signals, but not much.



Figure 10

Channel 2 in quadrant 1 is unique because the device is missing a solder ball in location J6, so this quadrant will be routed manually like channel 5.

The next step is to slide seven vias into channel 2 using a pattern similar to the vias in channel 5.

The placement of the first seven vias is shown in Figure 11.



Figure 11

There is additional area in channel 2 because of missing solder balls J6 and G7, so two additional vias will be added in this area. The via placed in location J6 will cause a DRC error when quadrant 1 is copied into quadrants 2, 3, and 4, but they will be removed later.

Also top-side routing is added to the vias in channel 2 as shown in Figure 12.



Figure 12

Now we can route the bottom-side traces to all vias previously placed in channels 2 - 5.

Figure 13 shows the top-side and bottom-side routing of channels 2 - 5.

The four vias in channel 2 without any top-side routing and the inside via of channels 1, 5, and 6 connect to internal power plane layers which will be connected to their respective power pads. Therefore, bottom-side routing is not required for these vias and the top-side routing will be discussed later.



Figure 13

Figure 14 shows a detail of the bottom-side routing.



Figure 14

The next step is to copy all top-side traces, vias, and bottom-side traces from channel 5 into channel 1. This is done by performing a copy followed by a move. The copy procedure rotates and copies channel 5 of quadrant 1 into channel 5 of quadrant 4 and the move procedure moves the results of the copy to channel 1 of quadrant 1.

This copy is done using the following procedure:

1. Select the copy command.

2. Select all vias and traces in channel 5 of quadrant1, as shown in Figure 15.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Right click and select "Rotate".

5. Move the cursor until the items being copied are rotated 90 degrees counter clockwise, then left click.

6. Right click and select "Snap pick to", "Symbol Origin".

7. Right click and select "Done".



Figure 15

This move is done using the following procedure:

1. Select the move command.

2. Select all vias and traces in channel 5 of quadrant4.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Select the pick box "P" in the lower right hand corner of the screen and enter the relative coordinate offset of "0 3.9".

5. Click the Pick button.

6. Click on the Close button.

7. Right click and select "Done".

The next step is copying channel 5 to channel 6.

This copy is done using the following procedure:

1. Select the copy command.

2. Select all vias and traces in channel 5.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Select the pick box "P" in the lower right hand corner of the screen and enter the relative coordinate offset of "1.95 0".

5. Click the Pick button.

6. Click on the Close button.

7. Right click and select "Done".

These steps complete most of the routing of quadrant 1 and final result is shown in Figure 16.



Figure 16

The next step is to copy all of the routing from quadrant 1 to quadrants 2, 3, and 4. This is done by using a procedure similar to a previously used copy procedure.

This copy is done using the following procedure:

1. Select the copy command.

2. Select all vias and traces in quadrant1.

3. Right click and select "Snap pick to", "Symbol Origin".

4. Right click and select "Rotate".

5. Move the cursor until the items being copied are rotated 90 degrees clockwise, then left click.

6. Right click and select "Snap pick to", "Symbol Origin".

7. Right click and select "Done".

Figure 17 shows the results of the quadrant 1 to quadrants 2 copy.



Figure 17

The previous copy procedure needs to repeated, by rotating the respective amount for each quadrant, to copy quadrant 1 to quadrants 3 and 4.

Figure 18 shows the results of the quadrant 1 to quadrant 3 copy.



Figure 18

Figure 19 shows the routing of all four quadrants.



Figure 19

The additional via added in location J6 of quadrant 1 will generate DRC errors when copied into quadrants 2 - 4. These extra vias needs to be deleted from quadrants 2, 3, and 4.

The three DRC errors generated can be seen in Figure 20.



Figure 20

If you haven ’ t already input the netlist from your schematic design, do so now. After the netlist has been imported, turn on the rat ’ s nest to see what you have left to route.

Now is a good time to delete traces that are connected to VDDS solder pads. VDDS solder pads should be connected directly to a power plane rather than connected through narrow traces since the inductance of the traces may cause undesirable voltage fluctuations.

Figure 21 shows some deleted VDDS traces that will be replaced with a direct via connections to the power plane. It also shows some preliminary routing for power and ground signals that will be filled in later with power and ground planes on the top layer.



Figure 21

Now it ’ s time to place the power and ground vias in the inner array. Like last time, place multiple vias in an unused area outside the package drawing and slide them to their final positions. Three vias will easily fit in each via channel of the inner array.

Figure 22 is a close up view that shows how these vias are placed and routing that makes it easier to see the various connections.



Figure 22

Ignore the extra ground and power shapes for now, they are just shown for clarity.

Focus on the yellow boxes and modifying the top layer routing to optimize these areas as shown in Figure 23. Note the middle of each side has an area where one extra top layer trace can escape. This is what we are now taking advantage of in these optimizations. By using these areas, those vias previously connected to external traces can be used to help share the power load.



Figure 23

Many engineers suggest one via should be placed near each power pad. What many don ’ t realize, if power pads are grouped together in the array and vias connecting power pads to their respective power plane are shared, bypass capacitors can be placed under the device instead of being placed outside the perimeter of the device. The additional inductance inserted by sharing vias is more than offset by the reduced inductance of placing bypass capacitors close to their respective solder pads. By grouping power pads in the array and sharing vias, decoupling capacitors can be placed under the device which minimizes PCB space and provides a more stable power source.

Some PCB designers may suggest thermal reliefs are not required for solder pads connected to power planes because BGA devices are soldered with a reflow oven and all parts on the top side of the PCB will be approximately the same temperature during the reflow procedure. This may be true, but thermal reliefs are shown here mainly to make the drawings easier to understand. TI recommends you discuss issues similar to this with your PCB assembly vendor to determine the best solution for your PCB design. By working with your PCB assembly vendor, a cost effective final product can be built with good yields and performance. If thermal reliefs are not used, it is suggested to open up the soldermask defined pad area to 0.35mm.

Figures 24, 25, and 26 show more areas (in yellow) to optimize as shown, and Figure 27 shows the overall end result.



Figure 24



Figure 25



Figure 26



Figure 27, Final outside routing after optimization.

Figure 28 shows only the bottom layer routing for clarity



Figure 28

Now we are ready to begin adding the power and ground shapes. There is some flexibility here. An example outline of each power and ground shape is shown in Figure 29. This figure shows how these shapes allow optimum grouping. Replicate these shapes in your design.



Figure 29

Figures 30, 31, 32, and 33 show close-up views of each quadrant.



Figure 30, Close-up view of power and ground shapes in quadrant 1.



Figure 31, Close-up view of power and ground shapes in quadrant 2.



Figure 32, Close-up view of power and ground shapes in quadrant 3.



Figure 33, Close-up view of power and ground shapes in quadrant 4.

One final note- It is possible to put vias with a large diameter pad between four solder pads connected to the same net since the copper pour in this area will replace the upper pad of the via. Putting vias with a 20 mil (0.5mm) pad between four 0.3mm solder pads of a 0.65mm pitch part would cause DRC errors because there is not 0.1mm of space on all sides of a pad this size. However, since the copper pour in this area replaces the pad on the top layer anyway, the size of the top layer pad is not important.

This means it ’ s possible to define a 16 mil (0.4mm) top layer pad diameter (that will fit in between four ball pads without a DRC) and 20 mil (0.5mm) lower and bottom layer pad diameters with a 10 mil (0.25mm) finished hole size and not violate most PCB fabricator rules.

By doing this it ’ s possible to insert additional power and ground vias which provide additional connections to the internal power and ground planes. The additional connections will provide a lower impedance power source for power pads.

The recommended via stack-up for this special via would be:

These vias can only be used between four solder pads of the same net where there is a shape (copper pour) that would normally fill the top layer area.

This is recommended if your PCB fabricator allows it. A few extra vias in areas that currently don ’ t have many may increase performance slightly (depending on the rest of your design).

Be sure to place the bypass capacitors as close to their respective power pads as possible.

Congratulations. Now you are done and ready to route the rest of your design!