AM3517/05 SDRC Subsystem

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The SDRAM Controller (SDRC) Subsystem provides connectivity between the processor and external mDDR and DDR2 SDRAM devices. It is a high-performance interface to 166MHz memory devices (faster memory devices my be connected, but they must be clocked at 166MHz). The AM3517/05 can interface up to 1GB of addressable space over 2 Chip Selects (512MB per CS) provided that the SDRC bus only sees 2 loads maximum. The SDRC comprises of two submodules:


 * SDRAM Memory Scheduler (SMS)
 * External Memory InterFace (EMIF)



SDRAM Memory Scheduler (SMS)
The SMS optimizes the SDRAM memory usage to provide The QoS level required by each of the initiators in the system and also adds a rotation engine (VRFB) to minimize the SDRAM page-miss penalty when accessing rotated lines in a graphic frame buffer.

External Memory Interface (EMIF)
The External Memory Interface (EMIF) is an Open Core Protocol (OCP) 2.2 compliant slave peripheral providing an interface to LPDDR or DDR2 SDRAM. The EMIF suooprts 16 or 32 bit data bus widths with 1GB of addressable space over 2 Chip Selects (512MB per CS). The SDRC bus supports a max of 2 loads.

Features

 * Open Core Protocol 2.2 (OCP) compliant.


 * Supports JEDEC standard compliant DDR2 and LPDDR1


 * 1GB total addressable space over 2 Chip Selects


 * Supports 16 and 32 bit SDRAM data bus widths


 * CAS latency
 * DDR2 - 2, 3, 4, 5, and 6
 * LPDDR1 - 2 and 3


 * Internal Banks
 * DDR2 - 1, 2, 4, and 8
 * LPDDR1 - 1, 2, and 4


 * Supports 256, 512, 1024, and 2048-word page sizes.


 * Burst Lengths
 * DDR2 - 8 (4 not supported)
 * LPDDR1 - 8 (2 and 4 not supported)


 * Supports sequential burst type.


 * SDRAM auto initialization from reset or configuration change.


 * Supports Bank Interleaving across both the chip selects.


 * Supports Clock Stop mode for LPDDR1 for low power


 * Supports Self Refresh and Precharge Power-Down modes for low power.


 * Supports Partial Array Self Refresh and Temperature Controlled Self Refresh modes for low power in LPDDR1.


 * Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip temperature sensor.


 * Supports ODT on DDR2.


 * Supports prioritized refresh.


 * Programmable SDRAM refresh rate and backlog counter.


 * Programmable SDRAM timing parameters.


 * Supports only little endian.

AM35x Hardware connections to SDRAM
This section will discuss the connections and recomendations for connecting to LPDDR1 and DDR2 memories. The AM35x SDRAM interface opperates at 166MHz allowing connection to 333DDR2 and 333LPDDR1 devices. The interface supports 1GByte over 2 Chip Selects. The SDRC signals should never exceed 2 loads. Some memories increase capacity by stacking dies in their packages. Each die in the memory device adds a load the the SDRC signals, so if a memory has 2 dies in the device then the AM35x SDRC signals will have 2 loads present.


 * Please visit the AM35x Schematic check list for more details on designing in the AM35x.
 * You can find schematics for the EVM fromLogicPD'ssite after creating an account and registering your board.
 * The OrCad Symbols can be found here.
 * The Allegro foorptrints can be found here.
 * The BSDL simulation model can be found here.
 * The IBIS simulation model can be found here.

DDR2
When connecting to DDR2, internal strobe gating should be used setting DDR_PHY_CTRL_1.CONFIG_EXT_STRBEN to 0. Also, memory buffer drive should be set to full drive strength (set SDRAM_CONFIG.REG_SDRAM_DRIVE to 0)

PCB Stackup
The minimum stackup required for routing the AM3517/05 is a six layer stack as shown in Table 6-17. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.

LPDDR1
When connecting to LPDDR, set DDR_PHY_CTRL_1.CONFIG_EXT_STRBEN to 1 to enable external strobe gating. External strobe gating compensates for external timing parameters on the board to ensure proper read timing. Ensure board routing recommendations in the AM35x Data Manual are followed when routing strobe enable signals STRBENx and STRBEN_DLYx.

PCB Stackup
The minimum stackup required for routing the AM3517/05 is a six layer stack as shown in Table 6-17. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.

SDRC Registers
To set up the AM35x SDRC registers please visit the wiki link below. This link provides key registere descriptions as well as a tool for calculating the proper values for the SDRC timing registers.

AM35x SDRC registers

Schematics

 * Key care abouts (Power vs ground, DDR supply)
 * Clock and DQS routing info
 * Schematics for eg. mDDR Interface
 * Schematics for DDR2 implementation
 * Routing Guidelines for DDR2
 * Routing Guidelines for mDDR

Software Design Support
Board Support Library files are available from Logic PD.

Useful Links

 * Sitara E2E forums
 * Sitara ARM® product page
 * AM35x Data manual
 * AM35x Technical Reference Manual (TRM
 * Memory vendor selection guide
 * AM35x Memory Subsystem wiki
 * AM35x Product Overview