AM335x GPMC to OMAP-L13x HPI Interface

= Introduction =

There are many types of embedded systems that require the combination of the AM335x applications processor with the OMAP-L13x DSP+ARM processor. In such systems it is often necessary to establish an inter-processor communication link for data and control message exchange between the two devices. The AM335x general purpose memory controller (GPMC) can be used with the OMAP-L13x host port interface (HPI) to establish a link suitable for inter-processor communication.

The OMAP-L13x HPI is a parallel bus that enables an external host processor, such as the AM335x, to access the memory addresses of the OMAP-L13x. The bus interface logic of the HPI is similar to that of an asynchronous NOR Flash memory making it compatible with the external memory interface of most host processors ; in this case the GPMC of AM335x. The OMAP-L13x HPI is often referred to as a “slave” interface, since it is not able to initiate transfers without an external host processor. Similarly, the AM335x can be referred to as the “master” of the interface since it initiates all transfers through its GPMC bus.

This document provides a summary of the significant information about AM335x GPMC to OMAP-L13x HPI interface and its timing analysis. This interface guide will be helpful to the users to understand the GPMC to HPI interface and its timing constraints.

The details about the GPMC and HPI interfaces are provided in the following links.
 * AM335x GPMC
 * OMAP-L1x HPI

= GPMC to HPI Interface =

GPMC to HPI Connectivity Diagram
The figure below shows the connectivity details between AM335x GPMC and OMAP-L1x HPI.



HPI Timing & Switching Characteristics
The below table provides the HPI timing requirements and its switching characteristics.

GPMC WAIT Sampling and Bus Turnaround
The details about the GPMC WAIT and bus turnaround are available in section 7.1.3.3.8.3 External Signals in AM335x TRM.
 * AM335x TRM

GPMC to HPI Read/Write Access
This section describes about the various timing parameters and timing diagrams of GPMC to HPI read and write accesses.

GPMC to HPI Read Timing Diagram
The figure below shows the timing details of GPMC to HPI Read access.



GPMC Read Timing Diagram
The figure below shows the timing details of GPMC Read access.



GPMC Read Timing Parameters
The below table provides the GPMC timing parameters for read access.

Assumption and Conclusion for Read Access

 * Analysis assumes 100MHz GPMC clock and OMAP-L1x CVdd = 1.1V or 1.2V.
 * The OE off time must be > Access time so that OE de-assertion is properly delayed by WAIT pin monitoring.
 * First and second half read timings are set identically because GPMC only provides one set of timings per CS.
 * Minimum read cycle time is 2 x 70ns = 140ns.
 * Peak read rate is (1/140ns)*4 bytes = 28.6MBytes/sec.

GPMC to HPI Write Timing Diagram
The figure below shows the timing details of GPMC to HPI Write access.



GPMC Write Timing Diagram
The figure below shows the timing details of GPMC Write access.



GPMC Write Timing Parameters
The below table provides the GPMC timing parameters for write access.

Assumption and Conclusion for Write Access

 * Analysis assumes 100MHz GPMC clock and OMAP-L1x CVdd = 1.1V or 1.2V.
 * The WE off time must be > Access time so that WE de-assertion is properly delayed by WAIT pin monitoring.
 * First and second half write timings are set identically because /HRDY can de-assert (not ready) in either cycle.
 * The BusTurnAround parameter must be used to insert at least one cycle between a read followed by a write.
 * Minimum write cycle time is 2 x 70ns = 140ns.
 * Peak write rate is (1/140ns)*4 bytes = 28.6MBytes/sec.