AM18XX SitaraWare SerialDevices

Important Note:

'The software found on this site is available for download, but is no longer being actively developed and maintained. This wiki is in maintenance mode and the software is supported on Sitara E2E forum'



AM18XX Serial Devices
AM18XX is integrated with the following serial devices
 * 1) Universal Asynchronous Receiver and Transmitter - UART
 * 2) Inter-Integrated Circuit Controller - I2C
 * 3) Serial Peripheral Interface Controller - SPI

SitaraWare contains the device abstraction layer for the above and also example applications which demonstrate the DAL. Following sections provide details about each of these DAL and examples.

UART
The UART component used in AM1808 is based on the industry standard TL16C550. AM1808 UART provides a FIFO of 16 bytes for the transmitter and the receiver sections for buffering the data and improves performance under slight latency conditions. UART also could be configured to generate DMA events to the DMA controller for transfer of data. However, for DMA mode to be functional the FIFO needs to be activated. The API functions exported to configure the UART and enable transmission and reception are listed in /include/uart.h

Interrupt Mode
These are the general guidelines for programming the UART.


 * UART needs to be first brought out of local reset by enabling the module in the Power Sleep Controller by using PSCModuleControl.
 * Pin multiplexing registers to enable the UART pins and a standard configuration is provided as part of the function UART2PinMuxSetup in platform directory.
 * Configure basic transfer parameters like baud rate, word length, no of stop bits, parity etc. The baud rate is configured based on the module input clock which is provided as a configuration input. This module input clock depends on the system/PLL configuration. UARTConfigSetExpClk is the first UART API to be called during initialization which sets these parameters.
 * The UART provides FIFO to buffer transmit and receive data and could be enabled if required. When the FIFO is enabled, the threshold levels to trigger receive interrupts need to be configured. UARTFIFOEnable could be used for enabling and resetting the FIFO contents. UARTFIFOLevelSet or UARTDMAEnable could be used for configuring the FIFO based on non-DMA mode or DMA mode of operation.

The UART status registers can be polled for transmission or reception readiness and error status. However, use of UART interrupts could be efficient to indicate readiness for data transfer and error status. In such a scenario, interrupt handler should be first registered and then the system interrupts and global interrupts should be enabled. UART peripheral interrupts can be enabled by UARTIntEnable in the last.

DMA Mode

 * In DMA mode of operation, the data transfer happens via EDMA. However, UART conditions, if needed, are handled by the interrupt handler/polling.
 * EDMA needs to be first brought out of local reset by enabling the module in the Power Sleep Controller by using PSCModuleControl for EDMA3 Channel controller and for EDMA3 Transfer controller.
 * EDMA is initialized using EDMA3Init, the DMA channels are mapped and enabled using EDMA3RequestChannel
 * EDMA PaRAM set (options) for UART transmit and receive are set using EDMA3SetPaRAM
 * EDMA transfer is enabled using EDMA3EnableTransfer.
 * UART DMA event generation for UART transmit and receive is enabled using UARTDMAEnable.
 * A transmit register empty/recieve byte condition generates a Tx/Rx EDMA event.
 * The EDMA completion interrupt occurs after number of bytes configured in the PaRAM set are exhausted.
 * The generation of UART EDMA events is disabled using UARTDMADisable
 * Two interrupt handlers are registered for EDMA
 * The completion interrupt handler EDMA3ComplHandlerIsr to take action on the completion of transfer. Action usually is to disable the channel on completion of transfer.
 * The error interrupt handler EDMA3CCErrHandler to take action on the error conditions. Action usually is to disable the channel, clear error bits and terminating the transfer
 * EDMA3FreeChannel will free the channels assigned to EDMA which will internally call EDMA3DisableTransfer to disable the transfer over UART EDMA channel.

Example application
The example application needs that the serial port on the EVM is connected to the host serial port via a NULL modem cable. A serial terminal application (like teraterm/hyperterminal/minicom) is running on the host. The host serial port is configured at 115200 baud, no parity, 1 stop bit and no flow control. Please ensure that the local echo setting for the terminal is turned off.

Interrupt mode

 * When the example application is loaded on the target and executed, a string "Sitaraware UART echo application" is printed on the serial terminal. After this it indefinitely, in a loop, expects characters input from the user on the serial terminal and echoes the same back on the terminal.
 * Modules used in this example
 * UART
 * Interrupt

DMA mode

 * When the example application is loaded on the target and executed, a message is printed on the terminal, expecting the user to input 20 characters. The application waits indefinitely for the input. Once the data is entered it is echoed back on the terminal.
 * Modules used in this example
 * UART
 * Interrupt
 * EDMA

I2C
The I2C component used in AM1808 is in complaint with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. The I2C module supports only Fast mode (upto 400 kbps) of operation. AM1808 I2C can be configured to multiple master-transmitters and slave-receivers mode and multiple slave-transmitters and master-receivers mode. AM1808 I2C also could be configured to generate DMA events to the DMA controller for transfer of data. The I2C driver library exports a set of APIs to configure and use I2C module for data transfers. The APIs are exported in /include/i2c.h

Interupt Mode

 * Configuring the I2C in master transmitter mode
 * I2C instance 0 is always on and does not require any powering up in the PSC module. However, I2C instance 1 requires powering up in the PSC module
 * The Pin multiplexing registers need to be configured for enabling the I2C_SDA and I2C_SCL pins.
 * The I2C is placed in local reset state using I2CMasterDisable
 * The required operating clock is set using I2CMasterInitExpClk.
 * The address of the slave to be addressed is set using I2CMasterSlaveAddrSet
 * The required I2C interrupts are enabled using I2CMasterIntEnableEx
 * The mode of operation is set using I2CMasterControl
 * In case of master transmitter mode of operation, the setting used is I2C_CFG_MST_TX. Optionally STOP, repeat mode also can be configured.
 * Only after the required settings the module is brought out of reset
 * Finally the data transfer is started by commanding a START on the bus using I2CMasterStart

DMA Mode

 * In DMA mode of operation, the data trasfer happens via EDMA. However, I2C conditions on the bus if needed to be handled are handled by the interrupt handler/polling.
 * EDMA needs to be first brought out of local reset by enabling the module in the Power Sleep Controller by using PSCModuleControl for EDMA3 Channel controller and for EDMA3 Transfer controller.
 * EDMA is initialized using EDMA3Init, the DMA channels are mapped and enabled using EDMA3RequestChannel
 * EDMA transfer is enabled using EDMA3EnableTransfer.
 * Upon I2C reset both tx and rx events are enabled. Thus rx and tx events are disabled by using I2CDMATxRxEventDisable.
 * EDMA PaRAM set (options) for I2C transmit are set using EDMA3SetPaRAM
 * I2C Tx DMA event generation is enabled using I2CDMATxEventEnable API.
 * A transmit empty register condition generates a trasmit EDMA event.
 * The EDMA completion interrupt occurs after number of bytes configured in the PaRAM set are exhausted.
 * The transfer over I2C EDMA channel is disabled using EDMA3DisableTransfer
 * The generation of I2C transmit EDMA event are disabled using I2CDMATxEventDisable
 * The EDMA interrupt status bit for I2C is cleared using EDMA3ErrClrIntr
 * Two interrupt handlers are registered for EDMA
 * The completion interrupt handler I2CEdmaIsr to take action on the completion of transfer. Action usually is to disable the channel, complete the transfer.
 * The error interrupt handler I2cEdmaErrIsr to take action on the error conditions. Action usually is to disable the channel, clear error bits and terminating the transfer

STOP condition generation

 * STOP can be configured to be automatically generated at the end of ICCNT number of bytes. In this case the I2C_CFG_STOP needs to be passed to I2CMasterControl and also the ICCNT should be updated with the required number of bytes using I2CSetDataCount
 * STOP can also be generated by manually. In this case I2C_CFG_STOP need not be supplied. But I2CMasterControl can be used to set STOP manually.
 * Various combinations decide the STOP generation. Please refer to the I2C Peripheral User Guide for more details.

Clocking constraints
This module input clock is derived from the PLL or Async domain clocks, which is 75MHz (for I2C1) or OSC frequency (I2C0) as per the SoC specification. I2C module imposes a contraint that the module input frequency is limited between 6.7MHz and 13.3MHz for proper operation, which is achived by a first level divisor, which is called the pre-scaler. The actual output clock or the operating clock frequency obtained by calculating the clock divisor as per the formula provided in the I2C peripheral user's guide.

Example Application

 * When the I2C example application is loaded and executed on the target, the LEDs on the EVM will blink for 100 times and then stop. This functionality is demonstrated in both DMA and interrupt mode of operation of the I2C controller


 * Modules used in this example
 * I2C
 * Interrupt

SPI
SPI Module supports SPI Clock frequency (SPI bus speed) between (SPI Module Clock)/3 to (SPI Module Clock)/256. AM1808 SPI supports Multiple Slave Chip Select I/O Pin, SPI Enable I/O Pin to improve overall throughput by adding hardware handshaking. AM1808 SPI could be configured to generate DMA event to EDMA controller for transfer of data. SPI device abstraction layer exports set of APIs to configure and use SPI Module for data transfers.

Interrupt Mode
Configuring SPI in Master Mode with Chip Select.


 * SPI needs to be first brought out of local reset by enabling the module in the Power Sleep Controller by using PSCModuleControl.'''
 * Pin multiplexing registers to enable the SPI pins(SIMO,SOMI,CLK,CS) and a standard configuration is provided as part of the function SPI1PinMuxSetup in platform directory.
 * The SPI is placed in local reset state using SPIReset.
 * The SPI is brought of reset state using SPIOutOfReset.
 * Configure SPI to operate in Master Mode using SPIModeConfigure.
 * The required Operating Clock is Set using SPIClkConfigure.
 * Configure SPI in 3PIN or 4PIN or 5PIN mode using SPIPinControl.
 * Configure the default value to be driven on the CS pin (line) when no transmission is performed SPIDefaultCSSet.
 * Configure SPI Clock’s Phase and Polarity Using SPIConfigClkFormat. The Clock Polarity and Phase configured needs to be compatible with clock requirements specified in flash device spec. For Example m25p80 spi flash requires active low (before and after data transfer clock is high) and in Phase Clock or active high (before and after data transfer clock is low) and out of Phase clock.
 * Configure SPI to Transmit MSB first during data transfer using SPIShiftMsbFirst.This configuration is done as per requirement of m25p80 spi flash requirement.
 * Set the Character length using SPICharLengthSet.
 * Selecting CS pin to be driven, Format Register to be used and asserting CS pin is achieved using SPIDat1config.
 * Map the required interrupts to the interrupt line INT1 using SPIIntLevelSet.
 * Enable the required interrupts using SPIIntEnable.
 * Enable SPI communication using SPIEnable.
 * Required data is written to SPI flash using SPITransmitData1 API.
 * Data is read from SPI flash using SPIDataReceive API.

DMA Mode

 * In DMA mode of operation, the data transfer happens via EDMA. However, SPI conditions like overrun errors etc, if required, are handled by the interrupt handler/polling.
 * EDMA needs to be first brought out of local reset by enabling the module in the Power Sleep Controller by using PSCModuleControl for EDMA3 Channel controller and for EDMA3 Transfer controller.
 * EDMA is initialized using EDMA3Init, the DMA channels are mapped and enabled using EDMA3RequestChannel
 * SPI module is enabled using SPIEnable.
 * EDMA PaRAM set (options) for SPI transmit are set using EDMA3SetPaRAM. It is to be noted that, since SPI is a transceiver device, transmit and receive EDMA parameters must be set before any transfer.
 * EDMA transfer is enabled using EDMA3EnableTransfer.
 * Chip Select(CS) line is forced to its active state before any transfer by calling SPIDat1Config with appropriate arguments.
 * SPI DMA event generation is enabled using SPIIntEnable.
 * A transmit register empty condition generates a transmit EDMA event and a receive event is generated when a byte is received in the receive register.
 * The EDMA completion interrupt occurs after number of bytes configured in the PaRAM set are exhausted.
 * There are two edma completions, one for receive and one for transmit.
 * Two interrupt handlers are registered for EDMA
 * The completion interrupt handler EDMA3ComplHandlerIsr to take action on the completion of transfer. Action usually is to disable the channel on completion of transfer.
 * The error interrupt handler EDMA3CCErrHandlerIsr to take action on the error conditions. Action usually is to disable the channel, clear error bits and terminate the transfer.
 * The generation of SPI transmit and receive EDMA events are disabled using SPIIntDisable.
 * Chip Select(CS) line is forced to inactive state by invoking the API SPIDat1Config with appropriate arguments.

Example application
Before executing the application, connect the UART port on the board to the serial communication port on the host PC through a NULL modem cable. Run a serial communication application (Tera Term/HyperTerminal/minicom) on the host. The host serial port is configured at 115200 baud, no parity, 1 stop bit and no flow control. Certain data is written to SPI flash using SPI bus. Then, the written data is read back. The read data is compared with the data that was written. If they get mathched, then an appropriate message gets displayed on the serial communication console. The same functionality is demonstrated in both DMA and interrupt mode of operation


 * Modules used in this example
 * SPI
 * UART
 * Interrupt
 * EDMA

Technical Support and Product Updates
For further information or to report any problems, contact sitaraware_support@list.ti.com