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AM35x EMAC/MDIO Module
Content is no longer maintained and is being kept for reference only!
- IEEE 802.3 compliant
- Synchronous 10/100 Mbit operation
- CBA3.1 compliant DMA controllers with VBUSP data transfers
- Selectable RMII Interface
- Hardware Error handling including CRC
- Little and Big Endian Support.
- Eight receive channels with VLAN tag discrimination for receive hardware QOS support.
- Eight transmit channels with round-robin or fixed priority for hardware QOS support.
- CPPI 3.0 compliant.
- EtherStats and 802.3Stats RMON statistics gathering.
- Transmit CRC generation selectable on a per channel basis.
- Broadcast frames selectable for reception on a single channel.
- Multicast frames selectable for reception on a single channel.
- Promiscuous receive mode selectable for reception on a single channel (all frames, all good frames, short frames, error frames).
- TI Adaptive Performance Optimization for improved half duplex performance.
- Configurable receive address matching/filtering.
- Emulation Support.
- EMAC Loopback Mode.
- 8K (2048 x 32) internal CPPI buffer descriptor memory.
- MDIO module for PHY Management.
- Programmable interrupt control with selected interrupt pacing.
Below is the layout between the processor, PHY, and the other remaining connections. This is not an exhaustive description, but should provide the necessary connections between the processor and PHY. There are many other design considerations that need to be understood, and should be described in further detail in the PHY's datasheet. Some of these further considerations include:
- Powering the PHY
- Providing a 50-MHz clock source as required by the RMII interface
- Pull-up/down requirements for any additional pins that are not used. For example, if the PHY also supports MII mode, there will be 2 more TXD and RXD pins.
- Requirements for connecting the PHY to the magnetics and LEDs
|RMII_TXD[1-0]||O||Transmit data (RMII_TXD). The transmit data pins are a collection of 2 bits of data. RMTDX0 is the least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only when RMII_TXEN is asserted.|
|RMII_TXEN||O||Transmit enable (RMII_TXEN). The transmit enable signal indicates that the RMII_TXD pins are generating data for use by the PHY. RMII_TXEN is synchronous to RMII_MHZ_50_CLK.|
|RMII_MHZ_50_CLK||I||RMII reference clock (RMII_MHZ_50_CLK). The reference clock is used to synchronize all RMII signals. RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz.|
|RMII_RXD[1=0]||I||Receive data (RMII_RXD). The receive data pins are a collection of 2 bits of data. RMRDX0 is the least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only when RMII_CRS_DV is asserted and RMII_RXER is deasserted.|
|RMII_CRS_DV||I||Carrier sense/receive data valid (RMII_CRS_DV). Multiplexed signal between carrier sense and receive data valid.|
|RMII_RXER||I||Receive error (RMII_RXER). The receive error signal is asserted to indicate that an error was detected in the received frame.|
|RMII_MDIO_CLK||O||Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).|
|RMII_MDIO_DATA||I/O||Management data input output (MDIO_D). The MDIO data pin drives PHY management data into and out of the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations.|
- You can find schematics for the EVM from LogicPD's site after creating an account and registering your board.
- Refer to the schematic review checklist when implementing your own design.
Symbols, Footprints, and Simulation Models
- The OrCad Symbols can be found here.
- The Allegro foorptrints can be found here.
- The BSDL simulation model can be found here.
- The IBIS simulation model can be found here.
Software Design Support
Linux drivers can be found as part of the u-boot source code in the PSP. Relevant functions are likely to be found in the following directories:
Some example code can be found from the BSL provided by logic PD. Specifically, the file evmam35xx_emac.c contains code for using the EMAC, including the following functions:
EMAC_init initialize the EMAC and MDIO for use EMAC_rx_packet receive a packet from the network EMAC_tx_packet transmit a packet on the network EMAC_phy_power_on power on the phy EMAC_phy_power_down power down the phy EMAC_phy_enter_loopback put the phy into loopback mode. EMAC_phy_exit_loopback remove the phy from loopback mode
There is an RMII loopback test located in the tests\experimenter\emac_loopback_rmii directory of the BSL. This test initializes the Ethernet PHY, places the PHY in loopback mode, and verifies that a packet can be transmitted successfully. Refer to the instructions foud in Doxygen\html\index.html for building and running the test.
These are the bandwitdth measurements from the PSP 3.00.00.03 datasheet.
|TCP Window Size
The performance numbers were captured using the iperf tool. Usage details are mentioned below:
- Server side command switch : "-s"
- Client side command : "-c <server ip> -w <window size> -d -t60"
- Iperf tool is run on the DUT1 in server mode and on DUT2 in client mode. Version 1.7.0 is used on both sides.
- Data captured here is for "iperf" in client mode.
- Cross cable is used to measure performance.
- Speed is set to 100Mbps
- Power Management disabled for measurement
- EMAC and MDIO Block Diagram
- How do I properly set the MAC address?
The MAC address must be manually set if you do not want Linux to assign a random one. A couple different unique addresses can be assigned, depending on your situation.
- If you're using the EVM from LogicPD, The simplest way to do this is to use the MAC address printed on the sticker located on the top side of the SOM. Note that this MAC address actually corresonds to the wireless 802.11b/g.
- If you cannot use the wireless MAC address, you can find the MAC address for the 10/100 Ethernet located in the CONTROL_FUSE_EMAC_LSB and CONTROL_FUSE_EMAC_MSB registers (addresses 0x4800 2380 and 0x4800 2384, respectively).
To set the MAC address, add the following line to the bootargs in u-boot.
- Are Gigabit transfer rates supported?
- No, due to the small 3-cell transmit and receive FIFO’s.
- Does the EMAC interface comply with IEEE 802.3 standards?
- Yes, except for the way it handles transmit underflow errors. Instead of using the Transmit Coding Error signal MTXER, the EMAC MII interface intentionally generates an incorrect checksum by inverting the CRC frame, so that the transmitted frame is detected as an error by the network.
- Clock Control
- All EMAC logic is clocked on one synchronous clock domain.
- The RMII interface frequency for the transmit and receive clocks are fixed at 50 MHz for both 10 Mbps and 100 Mbps. These clock sources are provided by the external PHY.
- Can I boot over Ethernet?
- Yes, the ROM code supports booting over the network. See section 126.96.36.199 of the TRM for further details. The following conditions must be met for using Ethernet boot:
- The EMAC is configured for full duplex, 100MBPS mode.
- Once the switch has been configured, the ROM code sends broadcasts to the ASIC ID on the LAN using a UDP datagram.
- The ASIC ID packet is sent only once. The server then responds with hex value 0xF003 0002 (Boot Message). The server then sends the size of the boot image.
- The server then sends the boot image binary.
- The MAC address is obtained from below control module registers:
- Ethernet MAC Address (LSB-24bits) --> 0x4800 2380 (Refer to system control module for more details.)
- Ethernet MAC Address (MSB-24bits) --> 0x4800 2384 (Refer to system control module for more details.)
- The download address & max size of images used for EMAC boot are exactly the same as USB/UART boot.
- Are both big and little Endian mode supported?
- Yes. Please refer to section 188.8.131.52 of the TRM for further details.
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