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AM35x with TPS65023: Design In Guide
Content is no longer maintained and is being kept for reference only!
- 1 Introduction
- 2 Power Requirements and Features of AM35x
- 3 TPS65023 Design-In Considerations
This design-in guide describes a power solution for the AM35x processor based on the TPS65023 device from Texas Instruments. This guide can be used to evaluate this solution for your design, or help you make decisions when designing in this solution.
Power Requirements and Features of AM35x
A TPS65023 based power solution can power any device in the AM35x family. The following section describes the specifications and power management features of the AM35x devices.
The following table details the power requirements for each AM35x device that is supported by a TPS65023 based power solution. Note that the only difference in power lies in the amount of current required by the VDD_CORE voltage rails. Otherwise, the specs are identical.
AM3505 and AM3517
|Power Rail||Voltage||Tolerance||Imax (mA)|
|VDDSHV||1.8V, 3.3V||+/- 5%||300|
The figure below shows the power-up sequencing requirements of AM35x. Here is a description of the power-up sequence:
3.3V Operation Sequence
1. IO 1.8V (VDDS, VDDS_SRAM_CORE_BG,VDDS_SRAM_MPU) supplies should come up first. This is required to bias the circuitry for the 3.3V IOs.
2. IO 3.3V (VDDSHV) supply should be ramped up next.
3. Core supply follows next (VDDS_CORE).
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST)
5. If using DAC, VDDA_DAC can be ramped along with the PLLs, or to conserve power, can be ramped on an as needed basis during application execution
6. If the onchip USB PHY is being used, VDDA1P8V_USBPHY can be ramped along with the PLLs, or to conserve power, can be ramped on an as needed basis during application execution.
7. When using USB, VDDA3P3V_USBPHY would be ramped next (or ramped after VDDA1P8V_USBPHY if using on an as needed basis)
8. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the 32KHz and HF clocks are stable.
1.8V Operation Sequence
1. IO 1.8V (VDDS, VDDSHV, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) supplies should come up first.
2. Core supply follows next (VDD_CORE).
3. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and complex IO power supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.
4. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the 32KHz and HF clocks are stable.
Power Down Sequencing
When using the TPS65023 power solution, power down is achieved by removing the input voltage VBAT. When this occurs, all voltages will ramp down at the same time, and the ramp rate of each voltage will generally be determined by the load on that voltage.
During power down, all signals driving AM35x should have a voltage level equal or less than the I/O voltage of AM35x to avoid driving pins that are unpowered. For example, the 32KHz clock should be gated by the VDDSHV signal. This ensures that this clock circuit does not drive the AM35x input clock pins when the VDDSHV is removed from AM35x.
TPS65023 Design-In Considerations
Below is a block diagram of one example of a complete power solution using the TPS65023 devices to power AM35x. The rest of the section will detail each design consideration to tailor the power solution to your needs.
A TPS65023 based power solution integrates many different power sources required to power up AM35x devices:
- contains 3 DCDC converters and 2 LDOs with enough supply current for all AM35x family devices
- Each DCDC converter and the LDOs can be sequenced using external sense signals and enables.
- The second LDO inside TPS65023 can be used to power AM35x USB or VDAC.
- Provides adjustable reset circuitry to control reset timing.
- provides adequate default voltages on power up
- provides I2C control of VDD_CORE voltage rail.
SYS_nRESPWRON rise time
It is better to have as less a rise time as possible to avoid any noise coupling, glitches on SYS_nRESPWRON signal.
The TPS65023 RESPWRON output is open drain, and requires a buffer or gate with fast rise time to meet the AM35x requirement. If multiple reset sources are needed, you can use an AND gate as shown below to provide fast rise time for all reset sources.
Typical 32KHz oscillators on the market can have up to a 1 second maximum to stabilize. This poses a challenge in the power up sequencing in that the reset signal must be maintained low throughout this stabilization time in order to properly reset AM35x. You can achieve this lengthy reset time using the TRESPWRON input of TPS65023. Consult the TPS65023 data manual for detailed information. By connecting a capacitor to ground to this signal, you can adjust the delay time of the reset output RESPWRON.
For example, to achieve a 1sec reset delay, you can use a 10nF capacitor to ground. Please refer to the TPS65023 data sheet for more detailed information.
Clock rise/fall time
AM35x clocks (both 32KHz and 26MHz clock) also have strict rise/fall requirements.
In order to meet these rise/fall times, a push-pull buffer is required to provide a faster edge on both clocks. Refer to the diagrams in the sections below.
When using an external oscillator for the 26MHz clock, AM35x SYS_CLKREQ signal is used to request the high frequency clock. This signal can be used to gate the clock on power up while OMAP35x is going through its power up sequence.
Generally, the 32KHz oscillator will be powered off the VDDSHV supply. This should be used as a condition before applying the 32KHz to the I/Os of AM35x.
32KHz clock circuit
If the 32KHz oscillator you choose exceeds the rise/fall time limit, a push-pull output buffer should be used to create a faster edge. Generally, the 32KHz oscillator will be powered off the VDDSHV supply. This should be used as a gating condition before applying the 32KHz to the I/Os of AM35x.
Alternatively, you can use the method found on the AM35x EVM, which uses a buffer to level shift the clock signal going to AM35x based on VDDSHV voltage.
High Frequency Clock circuit
AM35x requires a high frequency clock for normal operation. When using a 26MHz oscillator, AM35x only has strict rise/fall time restrictions of less than 10ns.
In order to meet these requirements, a push-pull buffer may be required before the clock input of AM35x.
For applications requiring VDAC voltage, you can supply VDDA_VDAC in one of two ways:
- Use one of the TPS650732 LDOs. Each LDO provides 200mA of current. The block diagrams above show this LDO powering both VDDA_DAC and USB voltages. But depending on you application, you can separate these out (using an external LDO) to provide more flexibility in powering on/off as each peripheral module is used.
- Use an external LDO. For example, TPS72118 provides proper 1.8V, 150mA maximum current. By connecting an AM35x GPIO, you can enable/disable this power source as the application needs it. An example schematic is below.
If you are not using the video DAC on AM35x, you do not need to power VDDA_DAC (tie it low through a 5Kohm resistor).
For applications requiring USB0 port, you need to supply VDDA1P8V_USBPHY with 1.8V and VDDA3P3V_USBPHY with 3.3V. Use an external 3.3V LDO for VDDA3P3V_USBPHY. And you can use one of the LDOs on the TPS65023 for 1.8V power. It is recommended that you combine the voltage source for VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE, but that source should not power other 1.8V supplies (ie, 1.8V for USB or VDAC)
The TPS65023 and AM35x are designed into the AM35x EVM SOM (System on Module) developed by LogicPD. You can follow the links to their website for information on the EVM and documentation (including schematics).
Source code for TPS65023 with the AM35x EVM can be found with PSP releases at PSP git repository