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AM35x with TPS650732: Design In Guide
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- 1 Abstract
- 2 Introduction
- 3 Power Requirements and Features of AM35x
- 4 TPS650732 Design-In Considerations
This document details the design considerations of a Power Management Unit solution for the AM35x processor using the TPS650732.
This design-in guide describes a power solution for the AM35x processor based on the TPS650732 device from Texas Instruments. This guide can be used to evaluate this solution for your design, or help you make decisions when designing in this solution.
Power Requirements and Features of AM35x
A TPS650732 based power solution can power any device in the AM35x family. The following section describes the specifications and power management features of the AM35x devices.
The following table details the power requirements for each AM35x device that is supported by a TPS650732 based power solution. Note that the only difference in power lies in the amount of current required by the VDD_CORE voltage rails. Otherwise, the specs are identical.
AM3505 and AM3517
|Power Rail||Voltage||Tolerance||Imax (mA)|
|VDDSHV||1.8V, 3.3V||+/- 5%||300|
The figure below shows the power-up sequencing requirements of AM35x. Here is a description of the power-up sequence:
3.3V Operation Sequence
1. IO 1.8V (VDDS) supply should come up first. This is required to bias the circuitry for the 3.3V IOs.
2. IO 3.3V (VDDSHV) supply should be ramped up next.
3. Band-gap, LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) should be ramped up next.
4. Core supply follows next.
5. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) should be ramped up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.
6. All the other complex IO power supplies should be ramped up next (VDDA_DAC, VDDA1P8V_USBPHY,VDDA3P3V_USBPHY).
7. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the 32KHz and HF clocks are stable.
1.8V Operation Sequence
1. IO 1.8V (VDDS and VDDSHV) supply should come up first. This is required to bias the circuitry for the 3.3V IOs.
2. Band-gap, LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) should be ramped up next.
3. Core supply follows next.
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) should be ramped up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.
5. All the other complex IO power supplies should be ramped up next (DAC, DSI, USB).
6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the 32KHz and HF clocks are stable.
7. The other power supplies can then be turned on upon software request.
Notes: Depending on the target Power IC
- VDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU can be grouped and powered up together.
- VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_HOST and all the other complex IO power supplies can be grouped together.
Power Down Sequencing
When using the TPS650732 power solution, power down is achieved by setting POWER_ON input to 0. When this occurs, all voltages will ramp down at the same time, and the ramp rate of each voltage will generally be determined by the load on that voltage.
During power down, all signals driving AM35x should have a voltage level equal or less than the I/O voltage of AM35x to avoid driving pins that are unpowered. For example, the 32KHz clock should be gated by the VDDSHV signal. This ensures that this clock circuit does not drive the AM35x input clock pins when the VDDSHV is removed from AM35x.
TPS650732 Design-In Considerations
There are 2 example block diagrams of a complete power solution using the TPS650732 below. One shows operating the AM35x with 3.3V I/Os, and the other shows AM35x with 1.8V I/Os. The rest of the section will detail each design consideration to tailor the power solution to your needs.
A TPS650732 based power solution integrates many different power sources required to power up AM35x devices.
The TPS650732 features the following benefits to make it an ideal PMIC for AM35x:
- Contains 3 DCDC converters and 2 LDOs with enough supply current for all AM35x family devices
- Automatically sequences the power sources without external circuitry. See above block diagrams for more details.
- The second LDO inside TPS650732 can be used to power AM35x USB or VDAC rail.
- provides adequate default voltages on power up
- provides I2C control of all power sources.
SYS_nRESPWRON rise time
It is better to have as less a rise time as possible to avoid any noise coupling, glitches on SYS_nRESPWRON signal.
The TPS650732 PGOOD output is open drain, and requires a buffer or gate with fast rise time to meet the AM35x requirement. If multiple reset sources are needed, you can use an AND gate as shown below to provide fast rise time for all reset sources.
Typical 32KHz oscillators on the market may require up to a 1 second maximum time to stabilize. This poses a challenge in the power up sequencing in that the reset signal must be maintained low throughout this stabilization time in order to properly reset AM35x. The TPS650732 PGOOD output includes a 400ms delay from the time the voltage sources are stable until the PGOOD signal transitions high. The PGOOD signal depends on the sources defined PGOODMASK in TPS650732 (the default sources are DCDC1, DCDC2 and DCDC3)
If you need a further delay in your reset signal, you have two options:
1. You can use the THRESHOLD and RESET signals of the TPS650732 to double the delay time of the reset to AM35x. The THRESHOLD input is compared to a 1V reference. Once this threshold is met, the RESET output transitions high after a 400ms delay. Thus, with the delay of 400ms for the PGOOD output, you can create a total delay of 800ms in SYS_nRESPWRON to further extend the time needed to stabilize.
2. You will need to add an external reset supervisor to further extend the length of the RESPWRON signal into AM35x. An example block diagram is below:
Clock rise/fall time
AM35x clocks (both 32KHz and 26MHz clock) also have strict rise/fall requirements.
In order to meet these rise/fall times, a push-pull buffer is required to provide a faster edge on both clocks. Refer to the diagrams in the sections below.
When using an external oscillator for the 26MHz clock, AM35x SYS_CLKREQ signal is used to request the high frequency clock. This signal can be used to gate the clock on power up while AM35x is going through its power up sequence.
Generally, the 32KHz oscillator will be powered off the VDDSHV supply. This should be used as a condition before applying the 32KHz to the I/Os of AM35x.
32KHz clock circuit
If the 32KHz oscillator you choose exceeds the rise/fall time limit, a push-pull output buffer should be used to create a faster edge. Generally, the 32KHz oscillator will be powered off the VDDSHV supply. This should be used as a gating condition before applying the 32KHz to the I/Os of AM35x. Alternatively, you can use the RESET output of the TPS650732 to provide a proper gating signal for this clock.
High Frequency Clock circuit
AM35x requires a high frequency clock for normal operation. When using a 26MHz oscillator, AM35x only has strict rise/fall time restrictions of less than 10ns.
In order to meet these requirements, a push-pull buffer may be required before the clock input of AM35x.
For applications requiring VDAC voltage, you can supply VDDA_VDAC in one of two ways:
- Use one of the TPS650732 LDOs. Each LDO provides 200mA of current. The block diagrams above show this LDO powering both VDDA_DAC and USB voltages. But depending on you application, you can separate these out (using an external LDO) to provide more flexibility in powering on/off as each peripheral module is used.
- Use an external LDO. For example, TPS72118 provides proper 1.8V, 150mA maximum current. By connecting an AM35x GPIO, you can enable/disable this power source as the application needs it. An example schematic is below.
If you are not using the video DAC on AM35x, you do not need to power VDDA_DAC (tie it low through a 5Kohm resistor).
For applications requiring USB0 port, you need to supply VDDA1P8V_USBPHY with 1.8V and VDDA3P3V_USBPHY with 3.3V. Use an external 3.3V LDO for VDDA3P3V_USBPHY. And you can use one of the LDOs on the TPS650732 for 1.8V power. It is recommended that you combine the voltage source for VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE, but that source should not power other 1.8V supplies (ie, 1.8V for USB or VDAC)
1.8V/3.3V VDDSHV voltage
For flexibility in I/O voltages, AM35x has the ability to use either 1.8V or 3.3V for its I/O. The voltage supplied to VDDSHV determines whether the AM35x operates its I/Os at 1.8V or 3.3V (see AM35x Data Manual for details on which I/Os have this flexibility).
The TPS650732 controls this voltage with the DEFDCDC2 signal (DCDC2 supplies VDDSHV).
- If DEFDCDC2 is low, DCDC2 outputs 1.8V
- If DEFDCDC2 is high DCDC2 outputs 3.3V
When VDDSHV is 1.8V, this saves an external LDO since VDDSHV can be combined with VDDS_SRAM_MPU. See block diagrams for more details.