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AM37x/DM37x Schematic Checklist
Content is no longer maintained and is being kept for reference only!
- 1 Introduction
- 2 Recommendations Specific to AM37x/DM37x
- 2.1 Critical Connections
- 2.2 Peripherals
- 2.3 If not used
- 3 General Recommendations
- 3.1 Before you begin
- 3.2 Critical Connections
- 3.3 Peripherals
- 3.4 Debug Considerations
- 3.5 Other
- 3.6 References
This article applies to the following devices:
Here are some links to schematics you can refer to:
- Beagleboard: http://beagleboard.org/resources
- AM37x EVM: http://www.mistralsolutions.com/assets/downloads/AM37x_EVM.php
If migrating a design from OMAP35x, you should review the OMAP35x To AM37x Hardware Migration Guide.
Recommendations Specific to AM37x/DM37x
- If using TPS659xx devices, please refer to the following app notes for more information on schematic and layout recommendations:
- Check decoupling capacitors (refer to the appropriate Data Manual for your device). Recommend 1 capacitor per 2 to 4 balls.
- VPP : should be left unconnected for production
- If using TPS6595x PMIC, SYS_OFFMODE should be connected to TPS6595x nSLEEP1
- If using TPS6595x PMIC, SYS_CLKREQ should be connected to TPS6595x CLKREQ. On OMAP3EVM, there is a pullup on this signal, but for proper low power functionality, this needs to be removed on the EVM, otherwise the 100K internal pull down in the TPS6595x did not adequately pull down this signal. SYS_CLKREQ is actively driven when the processor is requesting a high frequency clock, otherwise the signal is in high impedance. SYS_CLKREQ signal polarity is programmable using PRM_POLCTRL register, so ensure your external hardware matches the intended use of this signal.
- If using TPS65023, refer to the TPS65023 Design-In Wiki
- If using TPS65073, refer to the TPS65073 Design-In Wiki
- Typically, warm reset is used for a push button reset or reset from external circuits. Use a 4.7K pull up, and connect to nRESWARM on TPS659xx if using those PMICs.
- nSYSRESPWRON is connected directly to nRESPWRON on the TPS659xx devices. Be careful when connecting this to other reset sources (including push buttons). Generating a POR in this method could cause the TPS659xx devices to cut power because the warm reset sequence has not be programmed into the TPS659xx device, or the SLEEP sequence has not been programmed into the TPS659xx device. Typically, other reset sources should be connected to the warm reset.
If you are using POP memory
- Connect POP_INT0_FT and POP_INT1_FT to GPIOs to indicate POP die events to the processor
- Connect POP_TQ_TEMP_SENSE_FT to GPIO to monitor temperature of POP DDR
- Connect POP_RESET_RP_FT to SYS_NRESWARM to reset flash memories in the event of a warm reset.
- Check reset states of pins connected to other devices. Pins may have inadvertent states at or right after reset which may conflict with external devices. Especially check GPIOs connected to booting sources, so that these will be in the correct state when booting. Reset information per ball can be found in the Data Manual "Ball Characteristics" table. Check the columns Ball Reset State, Ball Reset Rel. State, and Reset Rel. Mode.
- SYS_CLKREQ is an open source type signal. You do have control of an internal pull up/down depending on the signal polarity, however an external pull up/down is recommended when this signal is used as an output to control an external oscillator or other clock source. An external pull down is recommended if you plan on using SYS_CLKREQ with active high polarity (PRM_POLCTRL.CLKREQ_POL=1). An external pull up is recommended if you plan on using SYS_CLKREQ with active low polarity (PRM_POLCTRL.CLKREQ_POL=0).
- Pull ups on SDA and SCL. 4.7K can be used. When implementing high speed I2C, lower values (470ohm) should be used.
- If using a TPS659xx device:
- I2C1 should be connected to TPS659xx I2C.CNTL control interface
- I2C4 must be connected to TPS659xx I2C.SR smart reflex interface
GPIO120-129 are 1.8V or 3.0V. These are the only GPIOs that are 3.0V capable. All others are 1.8V. Also check Additional Configuration for GPIO120-129 on OMAP35x (applicable for AM/DM37x) for further information.
The following GPIOs are input only: GPIO99,100,105,106,107,108,112,113,114,115
Different GPIOs are used to generate wakeup events based on which power domains are active:
- When only the WAKEUP power domain is active (ie, OFF mode), GPIO_1, 9, 10, 11, 30, and 31 can be used to generate a wakeup event.
- For the rest of the GPIOs in the GPIO1 module (GPIO_0-31, not include the ones above), they can only generate wakeup events if the CORE power domain is active.
- For GPIOs in modules GPIO2-6 (ie, GPIO_32-191), they can only generate wakeup events if the PER power domain is active.
Ensure that if you intend to use a GPIO as a wakeup event, you connect it to the appropriate GPIO signal.
- MMC_CLK : no pull ups needed
- MMC_CMD, MMC_DATx : 10K pull ups needed on each signal, unless using it in SDIO mode (eg., connected to a WLAN device) . Be sure to pull up to MMC voltage (on MMC1, that can be 1.8V or 3.0V)
- MMC1_CLK, MMC2_CLK and MMC3_CLK, series resistor is needed, place as close to the processor as possible. Recommended value is 33ohm, but will need to be adjusted based on trace length to the MMC peripheral.
- When using MMC1, VDDS_MMC1 supplies power for MMC1_DAT(0-3), and VDDS_X supplies power for MMC1_DAT(4:7). So if using 8-bit mode, both VDDS_MMC1 and VDDS_X need to be connected to the same power source. If using 1-bit or 4-bit mode, power to VDDS_MMC1 only needs to be applied. Pull VDDS_X low with 5-10K resistor if not using MMC1_DAT(4-7). In this scenario, you can use MMC1_DAT(4-7) for GPIOs, if needed. These can be supplied from a different power source on VDDS_X, depending on the voltage level you need for the GPIO (1.8V or 3.0V).
- If using MMC1_WP (write protect) and MMC1_CD (card detect) signals, they would typically be pulled up to 1.8V before connecting to the processor GPIO or TPS659xx GPIO. MMC1_CD can be used as a power saving feature to detect insertion of the card even when you have shut off the power via VDDS_MMC1 (or VDDS_X). Connecting it to TPS659xx device will allow it to turn on/off voltage upon insertion/removal of the card. Similarly, connecting MMC1_CD to the processor will allow for an interrupt to enable an external power source to turn on/off upon insertion/removal of the card.
- MMC2 and MMC3 interfaces are 1.8V only. You can connect MMC2 to 3.3V devices using an external transceiver (see block diagram in TRM). The transceiver must include a clock output that will connect to MMC2_CLKIN. MMC3 should only be used with 1.8V devices. It should not be connected through a transceiver.
- Also refer to SD-MMC Usage Notes wiki for more information
TV OUT interface
Refer to the TV out Application note.
- Refer to the Display Subsystem wiki for guidance on connecting the DSS.
- Add 10ohm series resistors to all data lines, HSYNC, VSYNC, ACBIAS, PCLK
- The DSS signal connection changes depending your PCLK.
Backward compatibility is maintained if your pixel clock on DSS interface is <= 60 MHz. But if your pixel clock is higher, 60< PCLK <= 75 MHz, you would need to use the High Speed Mode pinmux scheme. For all new AM/DM37x designs, High Speed Mode pinmux scheme should be used.
|Parallel mode 24-bit|
|Signal Name||PCLK <= 60 MHz [Legacy Mode]||PCLK <= 75 MHz [High Speed Mode]|
|VDDS||pwr rail VIO||pwr rail VIO|
- check to make sure any pullups for WAIT signals are 1.8V
- if used, ensure GPMC_CLK has 33ohm series resistor placed close to AM/DM37x
- Some McBSPs have different sized internal FIFOs. McBSP2 has 5K FIFO (others have only 512 bytes).
- McBSP2 and McBSP3 have sidetone capabilities.
- Place 33ohm series resistor close to AM/DM37x on all McBSP clock signals.
- for OTG operation, USB VBUS decoupling capacitance should be 1-6.5uF
- for device operation, USB VBUS decoupling capacitance should be < 10uF.
- for host operation, USB VBUS decoupling capacitance should be > 120uF
- ensure the VBUS decoupling capaciance is connected close to USB connector.
- ID signals should not be pulled down with a pull down resistor. If defaulting to an A-device, ground the ID signal on the USB PHY.
USB Host ports (HSUSB1 - HSUSB3)
- HSUSB3 will only support FS/LS USB PHYs.
- Review the AM37x Errata for issues concerning USB Host ports.
- For USB Host ports (USB1 and USB2), we recommend using TI's TUSB1210 USB PHY. This PHY supports input clocking mode (ie, the PHY is in slave mode and the processor sources the 60MHz ULPI clock). This device has recently been released and has been proven to work with AM/DM37x devices.
- Some layout recommendations for the TUSB1210
- Ensure trace length matching between all of the data signals and CLK and STP. Skew mismatch should be less than 10-20%
- Trace length of CLK is important. It should never be longer than the data signals. Layout the TUSB1210 so that the CLK pin faces the AM/DM37x device, so you can get the CLK the same or shorter (within 10-20%) than the data signals.
- Ideally, CLK and STP should be a close to the same length as possible.
- If using an SMSC3320, you must supply a dedicated low noise power source for 1.8V. This PHY is highly susceptible to noise on this rail and careful consideration must be used when designing with this part. Ideal reference design layout with this device can be found at the Beagle Board website.
- The TUSB1210 and SMSC3320 are pin-for-pin compatible, with some minor modifications. If you want to design your board to accomodate both, please see the following schematic, which details the changes that need to be made to the OMAP3EVM to change from the SMSC332x to the TUSB1210.
- Ensure that you follow the recommended layout guidelines and series termination values in section 6.4.2 of the Data Manual
- place 33ohm series resistor close to AM/DM37x on all MCSPI clock signals.
If not used
What to do with unused Power signals
- VDDA_DAC: if signals powered by VDDA_VDAC are not used, pull low with 5-10K resistor to ground.
- VDDS_MMC1/VDDS_X: if MMC1/MMC1a is not used, pull low with 5-10K resistor to ground. See MMC section above for more details
- VDDS_SDI: always connect this to 1.8V, even if SDI is not used. This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals. VDDS should should always be powered.
- VDDS_CSI2: if signals powered by VDDS_CSI2 are not used, pull low with 5-10K resistor to ground. This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals. VDDS should should always be powered.
- VDDS_CSIB: always connect this to 1.8V, even if CSIB is not used. This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals. VDDS should should always be powered.
- VDDS_DSI: always connect this to 1.8V, even if DSI is not used. This signal is called VDDS in the latest datasheets, and thus is combined with the other VDDS signals. VDDS should should always be powered.
- VDDS_X: if signals powered by VDDS_X are not used, pull low with 5-10K resistor to ground. This signal is called VDDS_X in the latest datasheets. See above for recommendations.
When the TV output is not required then the following configuration should be implemented in order to reduce the power consumption to its minimum value.
The analog pins tv_vref, vssa_dac, VDDA_DAC, tv_out1/2 and tv_vfb1/2 should be grounded. (Signal names appear as CVIDEO1_OUT, CVIDEO1_VFB, CVIDEO2_OUT, CVIDEO2_VFB, CVIDEO1_RSET in TRM SPRUGN4M)
To avoid internal current leakage, the following bits must be set to 0: DSS.DSS_CONTROL DAC_POWERDN_BGZ DSS.VENC_OUTPUT_CONTROL[2:0] PRCM.CM_FCLKEN_DSS EN_TV CONTROL.CONTROL_DEVCONF TVOUTBYPASS
THIS SECTION IS TRANSCLUDED FROM HARDWARE DESIGN CHECKLIST. ONLY INFO GENERIC TO ALL DEVICES BELONGS HERE SINCE IT APPEARS IN ALL SCHEMATIC CHECKLISTS.
Before you begin
Make sure you have the latest version of documentation, especially the data sheet and silicon errata.
TIP: Try searching the documentation for words such as: "must", "require", "do not", "shall", "note:", etc. Important criteria for the device will typically contain one or more of these words. This is an easy way to make sure you have not missed anything important.
TIP: - on each ti.com device product folder there is a button "Alert me about changes to this product". Registration here will enable proactive automatic notification of device errata.
Voltages from traces on a printed circuit board can couple to each other in places where it is not desired, (like power supply planes). To decouple the traces, we add capacitors to absorb some of the voltage and help reduce this effect. For more information on how to correctly place decoupling caps, see the data sheet section for power-supply decoupling.
PLL and some analog supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device side capacitor being the most important thing to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins farther away from each other may need their own filtered supply.
Are all requirements being met in terms of the order, delays, etc. of the power supplies?
Make sure your input clock/crystal meets the data sheet requirements. For example:
OSC Internal Oscillator Clock source
The figure below shows the recommended crystal circuit. It is recommended that pre-production printed circuit board (PCB) designs include the two optional resistors Rbias and Rs. They may be required for proper oscillator operation when combined with production crystal circuit components.
In general, adding Rbais and Rs resistors improves circuit performance by reducing the long start-up time, crystal overdrive and voltage and temperature related issues. Specifically, they provide the following functionality:
Rs helps reduce the drive level on the crystal and decreases the slew rate, which adds additional phase shift Recommended value: 50 Ohms Rbais (a.k.a. the feedback resistor) is used to bias the input of the inverting amplifier and improve the loop gain Recommended value: 1M Ohms
However, in most cases Rbias is not required and Rs is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs.
Please refer the below application note for calculation of Rs and RBais values:
Please refer the application note for the calculation of Rs and RBais values Crystek Application notes
Make sure that reset is kept asserted for the processor as the power supplies are ramping. You must not release the processor from reset until all the proper voltage/clocking is in place as specified by the data sheet. Conversely make sure that something on the board is actually RELEASING the reset once power and clocks are stable!
A useful tip is to place a 0.1uF cap near the reset pin to help avoid ESD-induced resets.
Also, you might want to have a reset button on your board as it can be helpful for development.
Although pin muxing is frequently software configurable, often the initial configuration is dependent on several configuration pins (e.g. are they high or low when reset is released). Make sure that the initial pin muxing corresponds properly with your boot modes so that any interfaces necessary for boot will be available. On some devices this could potentially be handled by the boot ROM, but to be certain you should configure the initial pin muxing appropriately.
DDR2 Routing Checklist
External Memory Interface (NOR/async)
The mapping of address pins to the memory interface is a device-specific detail that often depends on the bus width (8- or 16-bit data bus). For example in some devices the upper address bits get mapped down to handle the least significant bit while in other devices the pins may all "shift" depending on the width of the interface. Double check the documentation to verify the address mapping is handled correctly.
This simple peripheral is frequently hooked up incorrectly. Make sure it's connected as follows:
This is something often done incorrectly which can severely impact your ability to develop code!
For debugging purposes you may need to look at a signal on an oscilloscope. Therefore you'll want to make sure you can get access to the signals, particularly with BGA devices where it might otherwise be impossible. This can be done by bringing a via all the way through the board or other times where a pullup/pulldown is needed you can probe at the resistor. Having a GPIO brought to a test point or an LED can be useful as well.
Voltage Level Changes
Can you change the supply voltage with some simple resistor changes? Sometimes a pin-for-pin compatible release is made at a higher speed, sometimes requiring higher voltage and so having this flexibility on your board can save you trouble later.
Careful attention should be paid to any notes in the data sheet regarding the correct termination of pins. In particular make sure that termination instructions are exactly followed on reserved pins. Also, there are often pins that have special significance at the time the device reset is released. Often these are documented with something like "do not oppose this pin at reset" meaning that if there is an internal pullup or pulldown on that pin, you should not drive that pin in the opposite direction at reset. This would include not putting an opposing pullup/pulldown and also making sure that anything connected to that pin does not drive the pin opposite the intended direction.
For any unused pin you should pay attention to how it is terminated. Frequently pins will default to an input state and if they are left floating they may pick up noise and toggle at a high frequency. This can cause significant unwanted current consumption. Unused pins should be checked to see if they can be configured through software as outputs so they are not floating. If there is an internal pull-up/down you should configure the level of the output (high/low) to match the pull-up/down for lowest current consumption.
The ground symbols must have applicable names assigned to them. Also, the display field must be turned on so that the name of each ground symbol is displayed on the schematic to help in reviews to verify that no ground connections are orphaned by mistake. Use a standard triangle ground symbol for the main digital ground. Then use a signal ground (symbol with decreasing horizontal lines) for all other grounds. Use different names for these local grounds to allow easy review of the schematic as well as easy referral to them in the PCB layout tools.
The power symbols must have applicable names assigned to them. Also, the display field must be turned on to show the unique name for each power net. Placing a ‘V’ for the first character of a power supply can ease the schematic verification process since the power supply net names will appear next to each other in the view of the nets on the board.
This article began from spraa34 which was a design checklist for the DM642. It has been generalized a bit to make it more applicable to all designs.