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AM389x C6A816x DM816x Hardware Design Guide

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Hardware Design Timeline →[edit]

Constructing the Block Diagram Selecting the Boot Mode Confirming Pin Multiplexing Compatibility Confirming Electrical and Timing Compatibility Designing the Power Subsystem Designing the Clocking Subsystem Floorplanning the PCB Creating the Schematics Laying out the PCB Testing / Debugging

 

Introduction[edit]

Welcome to the Hardware Design Guide. The purpose of this guide is to walk hardware designers through the various stages of designing a board on this platform. The guide follows the structure shown in the Hardware Design Timeline above. Each design stage in the Timeline links to a collection of useful documentation, application notes, and design recommendations pertaining to that stage. Using this Guide, hardware designers can efficiently locate the resources they need at every step in the board design flow.

Constructing the Block Diagram[edit]

The first step in designing the hardware platform is to create a detailed block diagram.  The block diagram should contain all major system ICs and illustrate which I/O ports are used for device interconnection.  Below is a collection of resources to aid in the Block Diagram creation process.

  • The links at the TI website below provide block diagrams, application notes, tools, software, design considerations, and other related information for various Video and Imaging end-equipment products.
  • Select from a list of complementary devices to attach to AM389x, C6A816x or DM816x device in your system:
    • TBD

Selecting the Boot Mode[edit]

The block diagram should also indicate which interface will be used for booting this device.

  • These devices contain an on-chip ROM Bootloader:
    • The boot config pins are sampled at power-on-reset
    • Sets up system for boot depending on boot configuration selected
    • Depending on boot mode, copies image to internal RAM and then executes it
    • Maximum size of the boot image is 255KBytes (ROM uses 1KB internally)
  • The following boot modes are supported:
    • NOR Flash boot
    • NAND Flash boot
    • SPI boot
    • SD boot
    • EMAC boot
    • UART boot (PG2.0 only)
    • PCIe boot
    • If the first boot source fails to boot, the ROM will move on to the next one in the sequence. Keep in mind that some boot sources take some time to timeout if that boot source isn't available.
  • Key Boot Considerations:
    • It is recommended to include population options for other boot modes to aid in development
    • Boot pins have other functions after reset. Make sure your board design takes this into account when choosing pullup/down resistors for the boot pins.

Confirming Pin Multiplexing Compatibility[edit]

The device uses internal pin multiplexing to allow for maximum functionality in the smallest and lowest cost package. Due to this pin multiplexing, not all processor interfaces are always available simultaneously. See the Pin Multiplexing Control section and Terminal Functions section of the datasheet for complete details on the pin multiplexing.

  • Use the Pin MUX Utility tool to verify that the device pin multiplexing is compatible with your system block diagram. It is a Windows-based software tool that provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI processors, including: AM389x, AM35x, AM/DM37x, C6A816x, DM816x and OMAP35x Processors. Results are output as C header files in the format used by the U-BOOT initialization software found in the Linux Software Development Kit (EZSDK).

Confirming Electrical and Timing Compatibility[edit]

A key step in the hardware design before beginning schematic capture is to confirm both DC and AC electrical compatibility between this device and the other ICs connected to it.

  • The device datasheet has important information with regards to timing and electrical characteristics.
  • The preliminary IBIS model version is on this Forum thread: [1]
  • Note: TI provides PCB layout specifications for the following interfaces, eliminating the need to perform electrical analysis:
    • DDR2/3
    • SATA
    • PCIe
    • USB
    • HDMI

Designing the Power Subsystem[edit]

Once the block diagram has been validated for pin multiplexing, electrical, and timing compatibility, the power sub-system can be designed. See the below resources on estimating power consumption and designing a matching power subsystem.

  • Key Considerations:
    • Implementation of SmartReflex AVS to minimize power consumption on the voltage domains is required for proper device operation. Refer to device datasheet and TRM for more details. AVS FAQ
    • TI recommends using a fault-tolerant power supply design to protect against over-current conditions.
    • A heat dissipation solution is required for proper device operation.
    • Make sure to follow the supply sequencing requirements listed in the datasheet.
    • Make sure to properly filter the PLL power supply according to the recommendations listed in the datasheet.

Designing the Clocking Subsystem[edit]

In addition to the power subsystem, the clocking subsystem needs to be designed to provide appropriate clocks to all ICs in the system. These clocks can be created by pairing crystals with internal osciallators within the system ICs, or they can be created by a separate clock generator. See the below information on designing the clocking subsystem for your design.

  • Key Considerations:
    • The device operation requires a 27-MHz reference clock for operation.
    • A 100-MHz differential clock input is required for SATA and PCIe.
    • A third clock input is an optional 32.768-kHz clock input (no on-chip oscillator) for the RTC.
    • For more details, please refer to the Clocking sections of the device datasheet and TRM.

Floorplanning the PCB[edit]

Before beginning schematic capture, it is recommended to floorplan the system PCB to determine the interconnect distances between the various system ICs. See the below information on floorplanning your PCB.

  • TBD: Why and How to floorplan your PCB before starting schematic capture

Creating the Schematics[edit]

At this point in the design, it is time to start capturing the schematics. See the below collection of information to aid you in creating the schematics.

  • Key Considerations:
    • SDRAM (and other) output clocks are internally looped back
    • Don’t forget to install a JTAG connection
    • JTAG: Make sure to use the RTCK pin
  • It is often helpful to refer to example schematics throughout the schematic capture process: EVM Schematics
  • Make sure to use the canned schematics in the datasheet for the following interfaces:
    • DDR2/3
    • HDMI
    • SATA
  • For detailed information on USB board design, see the USB 2.0 Board Design and Layout Guidelines application report SPRAAR7
  • During and after schematic capture, check your design against the schematic checklist:

Below are Symbols, Footprints, and Simulation Models to aid in the design of the device placement and interconnects:

Laying out the PCB[edit]

After completing schematic capture, see the below information on laying out the PCB:

  • It is often helpful to refer to an example layout when designing a custom PCB: EVM Layout
  • Make sure to follow the Layout Specifications for the following Critical Interfaces:
    • DDR2/3 - See Datasheet
    • SATA - See Datasheet
    • PCIe - See Datasheet
    • Video DACs - See Datasheet
    • HDMI - See Datasheet
    • USB - See the USB 2.0 Board Design and Layout Guidelines application report SPRAAR7
  • The device's CYG package is designed with a new technology called a Via Channel™ array. This technology allows for easy routing of the device in two signal and two power layers using large through-hole via diameters and standard trace widths; it is cost and time effective. Where more than four printed circuit board (PCB) layers are used, the routing is much more open and flexible than a regular BGA. The Easy CYG Package PCB Escape Routing application report shows how to route the entire package by showing each quadrant up close and explaining the PCB feature sizes used.
  • General Information Articles:

Testing/Debugging[edit]

Once your custom PCB has been produced and assembled, refer to the below information on bringing-up and debugging the system.

  • Overview of Debug and Trace Tools
  • In these device platforms, other processors and accelerators are often treated as a black-box and most of the development and debugging is done on the ARM Cortex-A8 side.
  • Code Composer Studio
  • See the below information on using GEL Files to aid in configuring your design during debug/development. This can be used with CCS to print out useful debug information such as silicon revision, bootloader error messages, current PC and PSC states, and more.
  • Below are links to the BSDL Files for verifying PCB connectivity:
  • In addition, there are many useful wiki articles on debugging on this site, all you need to do is search. Many of these articles were written some time ago for various platforms that were available at that point; however, many are still applicable to other processors available today.
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