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Important Note:

This wiki is in maintenance mode and the information on this wiki may not be current. For questions regarding this device architecture, post questions on C64x Multi-core E2E forum

TMS320C6472 Wiki Page Content

What is the C6472?

  • A six-core, high-performance multicore DSP with the industry's best power efficiency, targeted for manufacturers of processing-intensive products on a strict power budget.
  • Available with six cores running at either 500MHz, 625MHz or 700MHz, and fully backward compatible with other DSP cores, the C6472:
    • Delivers up to 4.2 GHz of processing capability for high-end industrial applications and embedded systems where performance and energy efficiency are critical
    • Offers the industry's lowest power consumption with 3GHz performance at 0.15mW/MIPS for support of applications that drive many channels, demand maximum performance density and advanced functionality.
  • TI Whitepaper: Low Power Consumption and a Competitive Price Tag make the six-core TMS320C6472 ideal for high performance applications


What are the key features for C6472?

C6472 Block Digaram
  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320c64x+ DSP
    • 500/625/700 MHz
    • L1/L2 Memory Architecture:
      • 32K-Byte L1P Program RAM/Cache [Direct Mapped, Flexible Allocation]
      • 32K-Byte L1D RAM/Cache [2-Way Set-Associative, Flexible Allocation]
      • 608K-Byte L2 Unified Mapped RAM/Cache [4-Way Set-Associative, Fexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
  • EDMA Controller
  • Shared Memory Architecture
    • Shared L2 Memory Controller
    • 768K-Byte of RAM
    • Boot ROM
  • Three Telecom Serial Interface Ports (TSIPs)
    • Each TSIP is 8 Links of 8 Mbps per Direction
  • 32-bit DDR2 Memory Controller (DDR2-533 SDRAM)
    • 256 M-Byte x 2 Addressable Memory Space
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
  • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
  • 16-Bit Host-Port Interface (HPI)
  • One Inter-Integrated Circuit (I2C)
  • Six Shared 64-Bit General-Purpose Timers
  • 16 General-Purpose I/O (GPIO) Pins
  • 737-Pin Ball Grid Array (BGA) Package (ZTZ Suffix), 0.8-mm Ball Pitch
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [-40°C to 100°C]

When should I consider C6472?

  • If you are designing a processing intensive application but require low power and less heat
  • If you are using multiple single core DSPs per board, the C6472 is a viable migration option
  • If your application requires many cannels or maximum performance density
  • If your application must transfer of large amounts of data on/off chip.
  • If you are currently using ASICs or FPGAs, but are seeking a lower cost, software upgradeable option
  • If you are designing the following targeted applications:
    • Mission-critical applications such as military, aerospace, avionics, public safety, satellite and utilities systems
    • High-performance video and imaging applications
    • Emerging broadband and communications applications
    • Test & Measurement solutions
    • Cloud computing and blade servers
    • High end industrial
    • Multimedia server


What applications is the C6472 targeted for?

  • Applications using multiple single core DSPs per board (ie. DSP farm)
  • Applications that require transfer of large amounts of data on/off chip
  • Applications that drive many channels, demand maximum performance density and areas where designers require access to sophisticated functions.
  • Suitable applications include:
    • Mission critical applications such as military, aerospace, avionics, public safety, satellite and utilities systems
    • High performance video and imaging
    • Emerging broadband and communications
    • Test and measurement
    • Cloud computing and blade servers
    • High end industrial


What is the advantage of using C6472 in some of the mentioned applications?

  • C6472 delivers significant improvements in performance, integration and density, along with considerable efficiencies in power, cost and board space.
    • For instance, the C6472 integrates six 500 MHz DSP cores, a host of peripherals and internal memory on a compact 24mm by 24mm chip for DSP farm applications
  • When compared to six C6415 DSPs, a single C6472 DSP:
    • Consumes 40% less power
    • Costs 2/3 less in terms of DSP-related cost
    • Utilizes 80% less DSP footprint on-bard
  • TI also offers a range of development tools, support and code compatibility with previous DSPs to ease customer migration, including a low cost $349 EVM to evaluate C6472 performance.

6472-poweroptim.jpg 6472-pwrsavings.jpg

What peripherals are available for the C6472?

  • Gigabit Ethernet
  • Serial RapidIO (SRIO)
  • DDR2
  • Telecom Serial Interface Port (TSIP)
  • Host port interface (HPI)
  • Utopia
  • Inter-Integrated Circuit Bus (I2C)
  • General purpose input/output (GPIO)

What Analog solutions are available for the C6472?

To determine which TI Analog solutions are best suited for use alongside the C6472, please visit the Analog & Power for C6472 wiki page.

What Power Management solutions are available for the C6472?

The C6472 power will soon be live on TI's Analog & Power for Processors website as soon as the reference designs have been finalized. Until then below are a few devices that have been used in the designs.

The power reference designs were created with several key care-abouts in mind.

  • Number of C6472's: 1x or 8x
  • Input voltage range: 5V or 12V
  • Type of power parts used: DCDC Converters with Integrated FETs, DCDC Controllers, or Digital Power

The C6472 require regulated Core voltages of 1.0V/1.1V and 1.2V, I/O voltages of 1.8V and 3.3V, and Analog voltages of 1.8V and 1.2V.
These voltage rails are sequenced in the following order: 1) 3.3V I/O, 2) Core voltages, 3) 1.8V I/O and Analog voltages, 4) 1.2V Analog.

Below is a sampling of the power management products that complement C6472.

Part Number Description Details
4.5V to 18V Input, Low Pin Count, Synchronous Buck Controller with Power Good
  • Supports Pre-Biased Outputs
  • 600 kHz Switching Frequencies
  • High and Low side FET RDSON Current Sensing
  • 10-Pin 3 mm × 3 mm SON Package
5V Input 8A Synchronous Buck Converter with Integrated FETs and Sequencing
  • Power Up/Down Tracking For Sequencing
  • 30-mOhm, 12-A Peak MOSFET Switches for High Efficiency at 8-A Continuous Output Source or Sink Current
  • Wide PWM Frequency: Fixed 350 kHz or Adjustable 280 kHz to 700 kHz
  • Power Good and Enable
Digital Point of Load System Controller
  • Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM Controller
  • Controls Up To FourVoltage Rails and Up To Eight Phases
  • Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
  • Up To 1mV Closed Loop Resolution
Single Output LDO, 3.0A, Adj.(0.8 to 3.3V), Fast Transient Response, Programmable SoftStart
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9V with External Bias Supply
  • Ultra-Low Dropout: 115mV at 3.0A (typ)
  • Stable with Any or No Output Capacitor
3A Sink/Source DDR Termination Regulator
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications

What software and tools are available for the C6472?

C6472 EVM Digaram
  • C6472 EVM is a low cost, easy-to-use software debug platform for high performance application development. It includes:
    • Single C6472 processor
    • 256MB of 533 MHz DDR2
    • 64MB Nand Flash
    • 1 Mb I2C EEPROM for local boot (remote boot possible)
    • 2 RGMII 10/100/1000 Ethernet ports with MDIO
    • RS232 UART
    • Single module 170-pin AMC expansion for SRIO, TSIP, EMAC1, and I2C
    • C6455 EVM pin-compatible HPI daughter card connector
    • 2 user programmable LEDs and DIP SWs
    • 14-pin JTAG emulation with USB Host Interface (provided as an upgrade option)
    • Board-specific Code Composer Studio™ Integrated Development Environment
    • Simple setup
    • Includes design file such as Orcad, Gerber
    • Board support library accelerates software development on the EVM

How do I get access to the C6472 EVM?

What DSP Software Libraries are available for the C6472?

DSP Software examples and resources

TI 3rd Parties: C6472 Developer Network

Company Description
G.PAK Framework, G.168 Echo Cancellation, Conferencing, Transcoding SW
WhitePaper -- GPAK-C6472 A Rapid Way to Build High Density Voice Solutions
OSEck RTOS, LINX message layer, Network Protocols, System Visualization and debugging environments
Evaluate Now! -- High Performance DSP RTOS
Sundance DSP Two 6472 DSPS stand alone board with FPGA features TI CCS debugging environment
Surf Comm AMC form factor DSP farm for ATCA/uTCA. 2 DSPs per AMC card expandable to 4 AMC cards per board with Voice/Video SW Engine
Promentum ATCA-9100-TI ACTA media process blade features 2 mezzanine cards each host 10 C6472 DSPs.
White Paper -- Media Processing and Mobile Video Services
eInfochips C6472 EVM Vendor

Additional Information, Training, and Support

Where do I go for more information?
C6472 product folder (
C6472 EVM (
Where do I go for training?
C6472 Online Training Workshop (
TI Training website. See here (
Where do I go for support?
For further discussions and support go to TI\’s E2E Community (
TMS320C6000™ High Performance DSPs (
C6472 application notes (
Where can I download the lastest C6472 CSL?
You can get the latest revision of CSL here. (