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C64x+ CPU Cycle Accurate Simulator

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Important Note:

This wiki is in maintenance mode and the device architecture is supported on C64x Multi-core E2E forum

C64x+ CPU Cycle Accurate Simulator

This simulator is a C64x+ CPU only simulator and it's also cycle accurate simulator. This is generic C64x+ simulator & comes with a predefined configuration/memory map; Mainly used in algorithm development where the development is CPU centric.

Components Model

Components modeled in C64x+ CPU Cycle Accurate Simulator

  • C64x+ core, 2 timer models
  • Memory with single cycle latency.
  • Interrupts 4 -15 supported on the boundary

Note: Cache is not simulate in this simulator

Timer Model

The C6000™ DSP device has 32-bit general-purpose timers that can be used to: Time events, Count events, Generate pulses, Interrupt the CPU and Send synchronization events to the DMA.

Timer Memory Map

  • Timer0: Memory map - 0x01C21400 - 0x01C217FF
  • Timer1: Memory map - 0x01C21800 - 0x01C21BFF
  • Timer2: Memory map - 0x01C21C00 - 0x01C21FFF

Interrupt connection for Timer models

  • CPU pin 4 (Intsel_in_pin_4) to Timer_0 Event TIN12 (TIMER64_0_cpu_int_12)
  • CPU pin 5 (Intsel_in_pin_5) to Timer_0 Event TIN34 (TIMER64_0_cpu_int_34)
  • CPU pin 6 (Intsel_in_pin_6) to Timer_1 Event TIN12 (TIMER64_1_cpu_int_12)
  • CPU pin 7 (Intsel_in_pin_7) to Timer_1 Event TIN34 (TIMER64_1_cpu_int_34)

Simulator Configurable Options

C64x+ CPU Cycle Accurate Simulator can be configured to match other C64x+ device by configuring the timer. Follow the step to configure Timer model to different memory map & interrupt connection.

Simulator Configurable Options in CCSv4

  • Create a target configuration and select C64x+ CPU Cycle Accurate Simulator

C64x setup1.jpg

  • Goto Advanced Setup by clicking on the Advanced tab or Target Configuration link

C64x setup2.jpg

  • Select the appropriate Device memory map i.e the intended target device. If your Device is not listed select the closest one.

C64x setup3.jpg

  • Cache is by default disabled in this configuration. Cache can be enabled via drop down menu. (Note: Internally Simulator will change when cache enabled and is equivalent to C64x+ Megamodule Cycle Accurate Simulator or C64x+ Cycle Accurate Simulator)

Simulator Configurable Options in CCSv3.3

Simulator is configured via simulator configuration file in CCSv3.3. Please follow the step given below.

Timer Model configuration
  • Step 1: Go to CCS installation, and drivers folder. Open “simc64plus_cpu.cfg” configuration files. (Create a backup of file as precautions)
  • Step 2: Search for TIMER0_mif or TIMER1_mif, and go the locations.
   CONNECT1 C64xplus_mem_map, TIMER0_mif, 0x01C21400, 0x01C217FF, -0x01C21400;
   CONNECT2 C64xplus_mem_map, TIMER1_mif, 0x01C21800, 0x01C21BFF, -0x01C21800;

   Note: Last 3 hex values represent the start address, end address & offset.
  • Step 3: Change the start address, end address & offset for TIMER0 & TIMER1 accordingly.
   CONNECT1 C64xplus_mem_map, TIMER0_mif, start_address, end_address, -start_address;

  • Step 4: Mapping Timer TIN12 & TIN34 interrupt. Search for “TIMER64_0_cpu_int_12” & “TIMER64_0_cpu_int_34”.
   CONNECT23 C64xplus.INT4, TIMER0_cpu_int_12;
   CONNECT24 C64xplus.INT5, TIMER0_cpu_int_34;

  • Step 5: Change the CPU interrupt to the desired pin, by changing the interrupt number.
   CONNECT23 C64xplus.INT10, TIMER0_cpu_int_12;
   CONNECT24 C64xplus.INT12, TIMER0_cpu_int_34; 

   Note: C64x+ CPU Cycle Accurate simulator support interrupt 4-15 only.

  • Step 6: Repeat the Step 4 & 5 for Timer1 - “TIMER64_1_cpu_int_12” & “TIMER64_1_cpu_int_34”
  • Step 7: Save the configuration and bring up the simulator.
Runtime Memory Limit

Simulator support 64MB as memory limit for application, beyond that it gives an error. To increase the runtime memory limit add the following line in simulator configuration file inside Module C64xplus;

MODULE C64xplus;

      MEM_USAGE_LIMIT 100; // Supposing you want to change to 100 MB

END C64xplus;

Running Application

All BIOS application will run on simulator after selecting the appropriate devices which intern configure the timer memory map & interrupt configurations.

Note: In CCSv3.3 while running BIOS application check whether the simulator timer memory map & interrupt configuration matches the intended device.