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DM816x C6A816x AM389x DDR3 Init

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DDR3 Initialization with SW Leveling

ReadMe First

The purpose of this document is to describe the approach to fine tune the DDR PHY on all DM816x/C6A816x/AM389x devices with SW leveling.SW leveling can be done in two methods

  • Byte wise SW leveling (For 32 bit DDR interface only)

Data macro for each byte lane is leveled independently. The Slave ratio search program will calculate optimal values for each byte lane.

  • Word wise SW leveling (For 32 bit or 16 bit DDR interface)

The Slave ratio search program will calculate common optimal value that works for all four byte lanes.

Recommendation: It is advised to perform byte wise leveling to compensate for the trace length delays for each byte lanes accurately, especially at higher frequencies of operation as compared to the word wise leveling.

This wiki page talks about Byte wise SW leveling.For word wise SW leveling follow the link

Please refer to the attached presentation File:DDR3-Bring-up-Overview.pdf for an overview of the bring-up procedure.


  1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app
  2. CCS based program DDR3_SlaveRatio_ByteWiseSearch_TI816x.out which generates the static values for the software leveling process File:DDR3 SlaveRatio ByteWiseSearch
  3. TI816X GEL File File:TI816x
  4. TI816x U-Boot source code based on PSP release
  5. U-Boot User Guide which is a part of the PSP release
  6. CCS 5.1 or above installed on Windows XP with Service Pack 2
  7. Details of CCS 5.1 installation guidelines are given in

Download all the required files to the PC before proceeding to the next step.


In order to correctly setup DDR PHY on all DM816x/C6A816x/AM389x devices the approach used is Byte wise software leveling(To find the optimum DDR PHY slave ratio values for each byte lane).The DDR PHY has to be fine tuned based on the PCB trace lengths in order to compensate for the signal propagation delays accurately.

Important Note: SW leveling process is not intended to diagnose a non-working DDR interface. It is only intended for fine tuning the DDR PHY when the DDR interface is functionally working.

The leveling process involves the following steps

  1. Obtaining accurate PCB trace lengths (in inches) for the DDR CK trace and DQS trace (Data signal).
  2. Calculate the seed values to be input to the slave ratio search program ie:“DDR3_SlaveRatio_ByteWiseSearch_TI816x.out” as described in the subsequent sections.
  3. Configure the DDR controller (Also referred as EMIF) with the timing parameters calculated from the spreadsheet File:DM816x C6A816x AM389x EMIF4 Register based on the timing parameters mentioned in the data sheet of the specific DDR device being used.
  4. Configure the DDR PHY slave ratio registers with the respective seed values calculated from the spreadsheet.

Important Note: DDR memory access is expected to be working upon completion of the above mentioned steps. If not, choose a lower frequency of operation and repeat steps 1 to 4 until the basic memory access is working. It is meaningless to proceed further with SW leveling if the memory access is not working. Remaining steps will only help in getting the optimum DDR PHY slave ratio parameters.

5.Running the CCS based slave ratio search program on the device and collecting the optimum slave ratio values for the specific frequency of operation.

6.Programming the optimum values to the DDR PHY registers replacing the seed values that were programmed initially.

The slave ratio search program searches for the working range of the following Slave Ratio values based on the initial seed values keyed in on the command line,as explained in the next section.

  1. Read DQS Slave Ratio
  2. Read DQS Gate Slave Ratio
  3. Write DQS Slave Ratio

Please note that the DDR PHY has to be fine tuned each time when there is a change in the PCB layout(ie.when a new revision of the HW is made) or when the frequency of operation changes.

Obtaining the seed values

The seed values for the ratios may be obtained using the spreadsheet. The spreadsheet takes the following as inputs:

  1. DDR3 clock frequency
  2. CK and DQS trace lengths in inches for each of the byte lanes.

Excel screen.JPG

The user inputs should be entered on those cells that are marked green. Then spreadsheet will generate respective seed values at B17, B18 and B19 .These parameters should be passed to the CCS based slave ratio search program.

Running the CCS based slave ratio search program on the target hardware platform

Hardware and CCS Setup


You can skip this step if CCS is already configured. Make sure the settings are as mentioned in the configure step.

  • Connect the JTAG emulator to the TI816x using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
  • Make sure the Boot Mode / Configuration Select Switch are set to all 0s.
  • Start CCSv5.1 by navigating to 'Start' menu in Windows XP
  • Select the workspace folder where you want to store your project
  • Use target configuration file ti816x.ccxml. If there is a need to crate a new configuration, then follow steps below
    • Select new Target Configuration "View -> Target Configurations",Right click on "User Defined" folder then New Target Configurations
    • Connection = TI XDS560 Emulator
    • Board or Device = TI816x EVM (On some CCS versions you might have to use the internal name of TI816x or netra for this)
    • Save configuration, e.g., ti816x.ccxml
    • From next run, the project and target configuration will be readily available and can be skipped
  • Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
  • Select View -> Target Configurations. Look for the target configuration ti816x.ccxml created in the previous step
  • Right click and click "Launch Selected Configuration" this should launch debug session
  • In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
  • Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
  • Right click on the Cortex A8 core listed and click on "Connect Target"
  • A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Run menu and then click on Halt

Note: The steps mentioned above holds well for TI XDS560 Jtag emulator. User is advised to follow appropriate steps if a different emulator is being used

Generating the static values

Loading GEL File

  • Ensure that the GEL file File:TI816x is copied to the Windows Machine
  • Select Tools -> GEL Files in CCS
  • This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
  • Navigate to the directory containing gel file and select TI816x_ddr3.gel
  • A "Scripts" menu item (on top) should now be available
  • Select Script -> DM816x External Memories -> DDR3_400MHZ_doall
  • This will perform DDR3 initialization.
  • On success, you should see following at the CCS console:
CortexA8: Output: 	Device type is GP 
CortexA8: Output: 	DM816x Main PLL Init is in Progress, Please wait ..... 
CortexA8: Output: 	DM816x Main PLL Init is Done .....
CortexA8: Output: 	DM816x DDR PLL Init is in Progress for 400 MHz DDR Clock, Please wait .....
CortexA8: Output: 	DM816x DDR PLL Init is Done ..... 
CortexA8: Output: 	DM816x DDR2/3 PRCM Init is in progress ..... 
CortexA8: Output: 	DM816x DDR2/3 PRCM Init is Done ..... 
CortexA8: Output: 	Initializing EMIF1 ..... 
CortexA8: Output: 	DM816x EMIF Init is Done @ 400 MHz Clock Rate..... 
CortexA8: Output: 	PRCM for OCMCRAM0/1 Initialization in Progress 
CortexA8: Output: 	OCMCRAM0 & OCMCRAM1 Accesses are PASSED 
CortexA8: Output: 	PRCM for OCMCRAM0/1 Initialization in Done  
  • Note that sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the Slave Ratio Search Program

  • At this point, A8 in in user(USR) mode (marked as USR in the bottom right corner of CCS Status Bar). It needs to be in Supervisor(SPV) mode to run U-Boot and the Linux Kernel. Follow these steps:
  1. Goto menu View -> Registers
  2. Expand CPSR
  3. Select “M” and set it to 0x13
  4. These steps set the CPSR.M to 0x13 (SPV mode).
  5. Goto Tools -> ARM Advanced Features select NEON Enabled
  • Select Run -> Load -> Load Program. Select the CCS program DDR3_SlaveRatio_ByteWiseSearch_TI816x.out for loading.

Running the Slave Ratio Search Program


Enter 0 for DDR Controller 0 & 1 for DDR Controller 1

DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window

Enter the input file Name

Byte level Slave Ratio Search Program Values
                      BYTE3   BYTE2  BYTE1   BYTE0
Read DQS MAX           5d      60      78      77
Read DQS MIN            8       8       4       8
Read DQS OPT           32      34      31      38
Read DQS GATE MAX     1ec     1d1     1b5     1a0
Read DQS GATE MIN      8f      7c      63      41
Read DQS GATE OPT     13d     126     10c      f0
Write DQS MAX          97      a3      8c      8b
Write DQS MIN           0       0       0       0
Write DQS OPT          4b      51      46      45
===== END OF TEST =====  

Note : In the above example the output result gets saved in "Ti816x_Ratio_values.txt" file.


  1. SW leveling has to be performed on each EMIF separately and each PHY configured accordingly if the trace lengths are significantly different for each EMIF.
  2. The slave ratio program expects EMIF0 to be configured for a base address of 0x8000:0000 and EMIF1 to be at oxC000:0000. The DMM LISA registers has to be configured accordingly as shown in the File:TI816x gel file. Please note that user can choose a different base address for the DDR memory space (if needed) post the SW leveling.

The optimum slave ratio values may vary by small margin, if the SW leveling is performed multiple times. This is due to possible change in the environment variables such as Core/IO voltages and temperature.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR2/3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot for the software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

  • Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h.
  • At the top of the file add the #defines shown below as appropriate

#define CONFIG_TI816X_DDR3_400 /* Values supported 400,531,675,796 */
#define CONFIG_TI816X_DDR3_SW_LEVELING /* Enable software leveling as part of DDR3 init */
  • The values obtained in the previous step need to be plugged under the appropriate #define
Eg: For DDR3@796MHz
#define RD_DQS_GATE_LANE3       ((emif == 0) ? 0x160 : 0x15F) /*BYTE3 OPT values from CCS salve ratio*/
#define RD_DQS_GATE_LANE2       ((emif == 0) ? 0x178 : 0x171) /*BYTE2 OPT values from CCS salve ratio*/
#define RD_DQS_GATE_LANE1       ((emif == 0) ? 0x1B3 : 0x1B5) /*BYTE1 OPT values from CCS salve ratio*/
#define RD_DQS_GATE_LANE0       ((emif == 0) ? 0x1D6 : 0x1D3) /*BYTE0 OPT values from CCS salve ratio*/

#define RD_DQS_LANE3            ((emif == 0) ? 0x37 : 0x35) /*BYTE3 OPT values from CCS salve ratio*/
#define RD_DQS_LANE2            ((emif == 0) ? 0x37 : 0x43) /*BYTE2 OPT values from CCS salve ratio*/
#define RD_DQS_LANE1            ((emif == 0) ? 0x38 : 0x3F) /*BYTE1 OPT values from CCS salve ratio*/
#define RD_DQS_LANE0            ((emif == 0) ? 0x3B : 0x38) /*BYTE0 OPT values from CCS salve ratio*/

#define WR_DQS_LANE3            ((emif == 0) ? 0x7D : 0x6F) /*BYTE3 OPT values from CCS salve ratio*/
#define WR_DQS_LANE2            ((emif == 0) ? 0x8F : 0x87) /*BYTE2 OPT values from CCS salve ratio*/
#define WR_DQS_LANE1            ((emif == 0) ? 0xA2 : 0xA5) /*BYTE1 OPT values from CCS salve ratio*/
#define WR_DQS_LANE0            ((emif == 0) ? 0xB2 : 0xB0) /*BYTE0 OPT values from CCS salve ratio*/

Note that the values used here are for representative purposes only and based on the CCS app using Rev H TI8168 EVM. Use the values obtained from the CCS program over here

  • Open the file arch/arm/include/asm/arch-ti81xx/clocks_ti816x.h
#define DDR_PLL_796     /* Values supported 400,531,675,796 */
  • Open the file include/configs/ti8168_evm.hand make sure the following changes are there
#define CONFIG_TI816X_EVM_DDR3                  /* Configure DDR3 in U-Boot */
//#define CONFIG_TI816X_EVM_DDR2                /* Configure DDR2 in U-Boot */
  • Rebuild and flash U-Boot as described in the U-Boot user guide.

Run mtest

Simple memory test can be run from the U-Boot prompt using the mtest command. The syntax of the command mtest command is given below:

 mtest <start-address> <end-address> <test pattern> <# of iterations>

This command incrementally writes the test pattern to the memory range specified and then reads it back. Running the memory test with a few patterns should be sufficient for checking out the memory.

Run the memory test over the DDR address space of the EMIFs one by one:

 TI8168_EVM# mtest 0x80000000 0xA0000000 0xaa55aa55 3 (referred as Test A)
 TI8168_EVM# mtest 0xA0000000 0xC0000000 0xaa55aa55 3 (referred as Test B)

You can try different patterns (say all 0s, then all Fs and so on) to be sure of the memory reliability.

Interpreting the mtest result

  • Test A and Test B both pass consistently - Memory corruption can be ruled out
  • Test A passes but Test B fails - Only 512MB can be used if needed. The memory part needs to be changed
  • Test A fails but Test B passes - Only 512MB can be used if needed. The memory part needs to be changed
  • Test A and Test B both fail - The setup cannot be used. The memory part needs to be changed.