NOTICE: The Processors Wiki will End-of-Life in December of 2020. It is recommended to download any files or other content you may need that are hosted on processors.wiki.ti.com. The site is now set to read only.
Emulation Force Ready
- When a core is "hung", for example the RDY signal is asserted, the CPU is not able to continue execution. Emulation "Force Ready" artificially asserts the RDY signal to the core and immediately halts the CPU. This allows the debugger user to see the core registers.
- Emulation "Force Ready" is available for 64x, 64x+, and 647x cores only.
- This option is available when CCS detects that the CPU is "hung".
- After "force ready" the CPU pipeline has been flushed. Continued execution should not be attempted.
- Accessing memory regions may result in the cpu becoming "hung" again. This may be because the external memory may not be returning the RDY signal, thus causing the original hang.