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External Interface XINTF Type 1 FAQ for C2000

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This topic is a list of frequently asked questions that users have when using the External Memory Interface of type 1. XINTF type 1 is very similar to XINTF type 0 so many of the FAQ's will also apply here. This type is found on the 2833x, 2834x and 2843x devices. Refer to External_Interface_(XINTF)_Type_Differences for more information on type differences.

Electrical Specifications

Electrical specifications can change between devices, peripheral types and device families. Always refer to the data manual and errata for a particular device for Electrical Specifications.

This page is obsolete and no longer maintained. Refer to C2000 Real-Time Control Peripherals Reference Guide (spru566m) for peripheral type information.

--Lheustess (talk) 15:03, 27 July 2018 (CDT)

Refer to External_Interface_(XINTF)_Type_Differences for more information on type differences.

Frequently asked questions for XINTF Type 1

Q: When the external memory interface is enabled, how do the XINTF buses and control lines behave during accesses to internal memory?

The control signals would be placed in an inactive state if the CPU is accessing internal memory. These control signals are only activated when the CPU is accessing one of the 3 zones for the XINTF. There is a footnote in the timing diagrams of the XINTF that indicates the XA[] address bus holds the last address put on the bus during the inactive cycles. The XD[] data bus would go into a high-impedance state.

Q: Is there any need for pull-up or pull-down resistors to hold the external memory in a safe, inactive, state when the CPU is accessing internal memory?

The strobes will be forced to a high state and the address lines will hold their last value. There is no reason to put external pull-up's or pull-downs.

Q: Will the chip select line stay low during back-to-back accesses to the same zone?

Yes. Although keep in mind all accesses begin on the rising edge of XCLKOUT. For this reason, if there is a divider between XTIMCLK and XCLKOUT and the access ends on the falling edge of XCLKOUT, then there will be alignment cycle(s) between back-to-back reads where the chip select will go high. This alignment to wait for the next rising edge of XCLKOUT to start the next access.

Q: What if I need the chip select signal to go high between any two accesses?

If you are not using XREADY, then you can use the fact that all accesses begin on the rising edge of XCLKOUT to achieve this. Configure the timing such that an access will end on the falling edge of XCLKOUT. This will create the alignment cycle mentioned above. For example, if XCLKOUT is 1/2 XTIMCLK and the access time is an odd number of XTIMCLK cycles, then the access will always end on the falling edge of XCLKOUT. The XINTF will go inactive, including the chip select, until the next rising XCLKOUT edge.
If you are sampling XREADY, then there is no real way to control whether the number XTIMCLK cycles in an access is even or odd. In this case the chip select may stay active or it may go inactive depending on when XREADY indicates the external device has completed the operation. You could try adding delays between XINTF accesses in your application. In this case disabling the write buffer would help as well.

Q: Will the chip select line stay low during a DMA burst read from XINTF?

The chip select signal will only stay low if the reads are back-to-back (i.e. a new read is pending as the current read completes). The key is the DMA will not issue a read on each cycle. It is copying data so it will issue a read then write then read etc.. Minimum transfer time is 4 SYSCLKOUT cycles. Since there is a delay between the reads by the DMA the chip select signal will go high between the reads.

Q: Can I be sure that all read accesses terminate with the XRDn signal going high (inactive), even during back-to-back read operations?

Yes -
* XRDn is high during lead cycles - at least 1 lead is required for all accesses
* XRDn is low during the active cycles
* XRDn is high during trail cycles even for back-to-back accesses.
You can add more lead and trail time if you need XRDn to be high longer.

Q: I've noticed in Code Composer Studio GPAMUX2 and GPAMUX1 are written to after 'File>Load Program'. Why?

After reset these registers default to zero. The Code Composer Studio GEL script configures these GPIO's for external memory interface before a program load. This way the user can easily load code into the external memory. If this behavior is not desired it can be changed by removing the init XINTF function in the "OnPreFileLoaded" within the GEL file.

Q: I try to load code to XINTF using Code Composer Studio but I receive "Data varification failed at address 0x200000. Please verify target memory and memory map."

  • Make sure XINTF is enabled: You will need to enable the XINTF clock and configure the GPIO MUX registers for XINTF functionality before you can load to XINTF. There should be a funciton called XINTF_Enable() in the .gel file that will do this for you. In the default GEL files this function is inside OnReset() but is not enabled by default. To enable, just uncomment the call to XINTF_Enable().
  • Check if there is a data or address line not connected. Try doing a fill of memory with a value - if a Data line is not connected it will be reflected in the values read back. Address lines are a little tricker - you can use the CPU to fill the memory with a pattern to discover if an address line is not connected.
  • On the eZdsp the device may have moved in the socket. Carefully check that the device is well seated.

Q: I did a memory fill of a value, but the value read back is not correct.

  • Check the data lines: It's possible that a Data line is not making a good connection. On the eZdsp the device may have moved in the socket. Carefully check that the device is well seated.
  • Check XSIZE: Check that the XSIZE matches the configuration of the external memory on the board. Refer to the XINTF reference guide and the schematics for the board.
  • Make sure the Lead/Active/Trail values are not too short. Start with the default access which is quite long when checking the hardware connections.

Q: The XINTF_Enable() GEL function is handy, but I have to manually do it each time I load code, even if I didn't power cycle the device.

You can add the function to the "OnPreFileLoaded()" GEL function. This will tell Code Composer to execute this function before a file is loaded.

<syntaxhighlight lang=c> OnPreFileLoaded() {

   if (TxtOutCtl==0)
    GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
    GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers.");


Q: I don't understand what XSIZE does. Do I have to change it to 32 in order to do x32 writes/reads?

The XINTF XSIZE setting corresponds to how many data lines are used. In 16 bit mode there are 16 data lines. Working in this mode does not prevent you from doing a 32-bit read or write. If you do a 32-bit transfer then the XINTF will automatically break it into 2 16-bit accesses.

Q: I am using the 2833x eZdsp. I changed the example so XSIZE is x32 but now the example doesn't work. What is wrong?

When you switch to 32-bit mode then 32 data lines will be used. The physical connection to the RAM has to be correct for this mode as shown in the XINTF ref guide. On the eZdsp the external RAM is not connected in this manner so size 32 will not work because the high 16 data lines are not connected to memory. Refer to the eZdsp reference guide or schematics.

Q: I am using the 28346 Experimenters Kit. I am trying to use an example where XSIZE is 16 but it doesn't work. What is wrong?

Check the schematics for the board - the external memory RAM is connected in a x32 fashion on zone 7. In this configuration address line XA0 is a not used. So if you change the XINTF to XSIZE = 16 all even and odd word locations will look the same.