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OMAP3530 Power Estimation Spreadsheet

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Download OMAP3530_PowerEstimationSpreadsheet_v1_07.zip here.

Abstract[edit]

This article discusses the power consumption of the Texas Instruments OMAP3530 high-performance applications and multimedia processor. Power consumption on the OMAP3530 device is highly application-dependent, therefore a spreadsheet is provided to model power consumption for a user’s application and to present some measured scenarios. Version 1.x of the spreadsheet supports configurability of device core modules such as the ARM Cortex-A8, DSP and most peripherals. The data in the accompanying spreadsheet represents measurements and estimates for strong units, which are indicative of the expected maximums of power consumption for production units. Thus, the spreadsheet values may be used for board thermal analysis and power supply design as a maximum long-term average. The spreadsheet does not represent power savings possible with OMAP3530 SmartReflex features such dynamic power switching (DPS) or adaptive voltage scaling (AVS).

The data presented in the Version 1.x power estimation spreadsheet are based on measurements performed on OMAP3530 revision 3.0 silicon, as well as estimates.

The Power Estimation Spreadsheet[edit]

Version 1.07 is the latest version of the OMAP3530 Power Estimation Spreadsheet.

The spreadsheet applies to OMAP3530, OMAP3525, OMAP3515 and OMAP3503 devices.

Modeling Power for an Active Scenario[edit]

Power consumption estimates in the spreadsheet are separated by the major modules of the device, so that their contribution can be gauged independently of each other. The options in the spreadsheet are intended to provide some flexibility in customizing the worst case power consumption estimate for a specific application.

Power consumption in the OMAP3530 device consists of:

  • static power – due to leakage current, and dependent on temperature; and
  • active power – due to transistor switching, and independent of temperature.


Version 1.x of the OMAP3530 Power Estimation Spreadsheet models temperature effects on device power consumption. The user is allowed to specify an ambient temperature to be used in the power estimate. This is used to scale the baseline power estimate in the spreadsheet, which consists of device static power and power consumption from interconnects and clock trees.

Active power consumption is the power that is consumed by portions of the OMAP3530 that are performing some processing. Active power is independent of temperature, but dependent on voltage and module activity levels. Version 1.x of the OMAP3530 Power Estimation Spreadsheet allows configuration of activity for some modules in the OMAP3530 device. For other modules, measured scenarios are provided for the module, and the user is expected to select the usage scenario most closely aligned to the intended application.

Using the Power Estimation Spreadsheet[edit]

The Version 1.x power estimation spreadsheet consists of 5 sections: tables A, B, C, D and E. Using the power estimation spreadsheet involves simply entering appropriate usage parameters. Cells that are designed for user input are white in color. To use the spreadsheet, simply configure the white cells to a value most closely aligned with your intended scenario. The spreadsheet will display the details of power consumption for the configuration selected.

Briefly, the purpose of each of the 5 sections is:

  • Section A: configure the high-level system configuration such as ambient temperature and processors OPP.
  • Section B: baseline device power consumption due to static power, DPLLs, and L3 and L4 clock trees.
  • Section C: active power of ARM and IVA subsystem components.
  • Section D: active power of peripherals and graphics accelerator.
  • Section E: full chip power tally.


Section A: High-Level System Configuration[edit]

This section allows the user to set an ambient temperature (not junction temperature) between -20C and 85C, and an operating performance point (OPP) for the ARM and IVA subsystems, as shown in Figure 1.

Figure 1. Section A of OMAP3530 power estimation spreadsheet allows configuration of ambient temperature and processors' OPP.
Spreadsheet sectionA.JPG

The OPP options supported for the ARM and IVA subsystems voltage domain (VDD_MPU_IVA) are shown in Table 1 below.

Table 1. Operating performance point definitions for the processor subsystems.

Processors' OPP VDD_MPU_IVA (V) ARM MHz IVA MHz SYS_CLK MHz
1 0.975 (see Note 1) 125 90 26
2 1.05 250 180 26
3 1.20 500 360 26
4 1.27 550 400 26
5 1.35 600 430 26
6 1.35 720 520 26

Note 1: Measurements were done at VDD_MPU_IVA = 0.98V for OPP1.

For modules powered by the VDD_CORE rail, the default nominal OPP (OPP3) is assumed with the configuration for voltage and interconnect clocks shown in Table 2 below.
Table 2. OPP3 definition for VDD_CORE components.

Parameter Value
Interconnects/Peripherals OPP 3
VDD_CORE voltage 1.15V
CORE_CLK frequency 332MHz
L3_ICLK frequency 166MHz
L4_ICLK frequency 83MHz
SGX_ICLK frequency 110MHz
SDRC_CLK frequency 166MHz
GPMC_CLK frequency 83MHz
SYS_CLK frequency 26Mhz


The spreadsheet presents information for only the full-featured OMAP3530 device in OMAP35x family. However, since the spreadsheet breaks out the power consumption due to each module in the OMAP3530, estimates for the OMAP3525, OMAP3515 and OMAP3503 can be obtained by choosing the “N/A” or “off” option for the module not present in the device under consideration. This will ensure active power from the non-applicable module is not included in the power tally. The device differences are summarized as follows:

  • OMAP3530 (device with ARM, IVA and SGX)
  • OMAP3525 (device with ARM and IVA)
  • OMAP3515 (device with ARM and SGX)
  • OMAP3503 (ARM only device)


Section B: Baseline Core Power[edit]

This section represents the static leakage power of the device as well as the power consumption of the DPLLs and clock trees as shown in Figure 2. Although the OMAP35x family provides many clock- and power-gating features for reducing the idle time power consumption of unused portions of the chip, this spreadsheet does not support these power optimization features as it does not contain a PRCM model to capture and enforce any interdependencies among modules. The baseline core power section assumes clocks and power are turned on throughout the device all the time, and is not configurable.

Figure 2. Section B of the OMAP3530 Power Estimation Spreadsheet v1.0 presents the device baseline power (leakage, DPLLs, L3 and L4 interconnects and clock trees).
Spreadsheet sectionB.JPG

Section C: VDD_MPU_IVA/VDD1 (Modules Active Power)[edit]

This section is used to configure the activity on the ARM and IVA subsystems as shown in Figure 3. For each subsystem, a user can select a power profile and enter module utilization as a percentage.

Figure 3. Section C of the OMAP3530 Power Estimation Spreadsheet allows configuration of the ARM and IVA subsystem components for active power estimation.
Spreadsheet sectionC.JPG

For most modules, the following power profiles are included:

  • N/A – no active power contribution
  • Estimated max – maximum power from design simulations.


Power profiles for the ARM subsystem include:

  1. N/A – no active power contribution.
  2. Cortex-A8 + Neon (max estimation) – based on mA/MHz/V number for Cortex-A8 with Neon usage, obtained from design simulations.
  3. Dhrystone standalone (Cortex-A8, measured) – based on measurements done while running Dhrystone 2.1 on the Cortex-A8.
  4. Saxpy loop under Linux (Cortex-A8 + Neon, measured) – based on measurements done while running Saxpy loop executable compiled with Neon optimizations, under Linux.


Power profiles for the IVA subsystem include:

  1. N/A – no active power contribution.
  2. Estimates – based on mA/MHz/V numbers with margining, for the IVA subsystem components, obtained from design estimates.


Module utilization is the percentage of the available MHz at the selected OPP needed to meet the scenario processing requirement. A single utilization entry is provided for the ARM subsystem. For the IVA subsystem, a separate utilization entry is provided for each of the following IVA subsystem components:

  1. DSP (C64x+ Digital Signal Processor)
  2. iLF (improved Loop Filter)
  3. iME (improved Motion Estimator)
  4. iVLCD (improved Variable-Length Coder/Decoder)
  5. SEQ (Sequencer)


The ARM and IVA clock frequencies are set by the “Processors OPP” selection available in Section A.

Section D: VDD_CORE/VDD2 (Modules Active Power)[edit]

Section D enables a customized active power configuration for modules powered by the VDD_CORE or VDD2 supply rail in the OMAP3530 as shown in Figure 4 below.

Figure 4. Section D of the OMAP3530 Power Estimation Spreadsheet allows for the configuration of peripherals for active power estimation.
Spreadsheet sectionD.JPG

For each module, a drop-down menu of measured and estimated power profiles is provided. Details of the power profiles follow.

  • SGX (2D/3D graphics accelerator engine):
  1. N/A – no active power contribution.
  2. Rendering a 3D graphics frame (measured) – power measured on strong ES3.0 silicon for a test case involving continuous rendering of 1 frame from 3D graphics benchmark. SGX at 110MHz.
  3. Estimated max – maximum power from design simulations.


  • SDMA (system direct memory access controller):
  1. N/A – no active power contribution.
  2. 1-channel (same power as 4-channels) – power measured on strong ES3.0 silicon while SDMA transferring 512MB between internal memories, using 1 channel.
  3. Estimated max – maximum power from design estimates.


  • SDRC (SDRAM controller):
  1. N/A – no active power contribution.
  2. Estimated max – maximum power from design estimates.


  • GPMC (general purpose memory controller):
  1. N/A – no active power contribution.
  2. DMA Burst Write to Pseudo-SRAM over GPMC – power measured on strong ES3.0 silicon for a burst write over GPMC to external PSRAM device.
  3. DMA Burst Read from Pseudo-SRAM over GPMC – power measured on strong ES3.0 silicon for a burst read over GPMC to external PSRAM device.
  4. GPMC 50% Write, 50% Read, Pseudo-SRAM – 50% of 2) and 50% of 3 above.
  5. Estimated max – maximum power from design estimates.


  • DSS (display sub-system):
  1. N/A – no active power contribution.
  2. 27MHz PCLK, 800x480 display – power measured on strong ES3.0 silicon while DISPC graphics pipeline being used to output an image over an 18-bit interface at 27MHz pixel clock rate to an 800x480 display using the RFBI bypass mode. Vid pipelines not used.
  3. 54MHz PCLK, 800x480 display – power measured on strong ES3.0 silicon while DISPC graphics pipeline being used to output an image over an 18-bit interface at 54MHz pixel clock rate to an 800x480 display using the RFBI bypass mode. Vid pipelines not used.
  4. Estimated max – maximum power from design estimates.


  • CAM/ISP (camera/image signal processing sub-system):
  1. N/A – no active power contribution.
  2. DDR->ISP->DDR – power measured on strong ES3.0 silicon while the ISP is processing data from external memory and outputting to external memory. The CCP2 (compact camera port interface), CCDC (CCD/sensor capture front-end), PRV (Preview) and RSZ (Resizer) modules in the ISP are utilized as shown in the data flow diagram in Figure 5 below.
  3. VS6650CAM->ISP->DDR – power measured on strong ES3.0 silicon while data from VS6650 camera sensor being captured by the OMAP3530 camera input port, processed through the ISP modules and output to external memory as shown in the data flow diagram in Figure 6 below.
  4. Estimated max – maximum power from design estimates.


Figure 5. Data flow diagram for CAM/ISP test case where data source and destination is DDR memory.
Ddr isp ddr.JPG

Figure 6. Data flow diagram for CAM/ISP test case with image sensor as data source and DDR memory as data destination.
Cam isp ddr.JPG

  • USB (universal serial bus):
  1. N/A – no active power contribution.
  2. IN Bulk Transfer, From USBOTG (Device) to USBTLL_1 (Host) – power measured on strong ES3.0 silicon for bulk data transfers from USB-OTG port acting as device to USB-High Speed Host Controller Port1 acting as host, using transceiver-less link logic (TLL).
  3. OUT Bulk Transfer, From USBTLL_1 (Host) to USBOTG (Device) –power measured on strong ES3.0 silicon for bulk data transfers from USB-High Speed Host Controller Port1 acting as host to USB-OTG port acting as device, using transceiver-less link logic (TLL).
  4. Estimated max – maximum power from design estimates.


  • MMC (multimedia card host controller) 1, 2 and 3 have the same set of power profile options:
  1. N/A – no active power contribution.
  2. Estimated max – maximum power from design estimates.


  • McBSP (multi-channel buffered serial port) 1, 2, 3, 4 and 5 have the same set of power profile options:
  1. N/A – no active power contribution.
  2. 16MHz, 16MB transfer – power measured on strong ES3.0 silicon while McBSP module transferring 16MB data in loopback mode at 16MHz.
  3. 27MHz, 16MB transfer – power measured on strong ES3.0 silicon while McBSP module transferring 16MB data in loopback mode at 27MHz.
  4. 83MHz, 16MB transfer – power measured on strong ES3.0 silicon while McBSP module transferring 16MB data in loopback mode at 83MHz.
  5. Estimated max – maximum power from design estimates.


  • UART (universal asynchronous receiver/transmitter) 1, 2 and 3 have the same set of power profile options:
  1. N/A – no active power contribution.
  2. 115.2kbps – power measured on strong ES3.0 silicon while UART module functional at 115.2kpbs baud rate.


  • GPTIMERS (general purpose timers):
  1. N/A – no active power contribution.
  2. All on 32kHz clock – all GP timers enabled and running on 32kHz clock.
  3. All on SYSCLK – all GP timers enabled and running on system clock.


  • MISC. PERIPHERALS (other miscellaneous peripherals such as I2C, SPI and GPIO modules):
  1. N/A – no active power contribution.
  2. Estimated max – maximum power from design estimates.


Section E: FULL CHIP POWER TALLY[edit]

This section allows the user to obtain a power consumption estimate for the full chip. For each power supply rail available on the OMAP3530, a set of power profiles is provided in a drop-down menu.

Figure 7. Section E of the OMAP3530 Power Estimation Spreadsheet provides a full chip power consumption estimate.
Spreadsheet sectionE.JPG

Available power profiles for the various power rails on OMAP3530 are documented below. The Standby Modes 1, 2, 3 and 4 are defined as in Figure 8 and Figure 9. Note that:

  • VDD1 is the ARM and IVA subsystems voltage domain supplied by VDD_MPU_IVA rail,
  • VDD2 is the interconnects and peripherals voltage domain supplied by VDD_CORE rail,
  • VDD3 is the wakeup voltage domain powered by an embedded LDO supplied by the VDDS_WKUP_BG rail, and
  • VDD4 and VDD5 are the embedded memories voltage domains powered by embedded LDOs supplied by the VDDS_SRAM rail.


Figure 8. The states of VDD1, VDD2 and VDD3 voltage domains in OMAP3530 in 4 standby modes.
Stdby states vdd123.JPG

Figure 9. The states of VDD4 and VDD5 voltage domains in OMAP3530 in 4 standby modes.
Stdby states vdd45.JPG

Off-mode (or Device Off-mode) is the lowest power state from which the OMAP3530 can still wakeup autonomously. In this device state all domains are powered off except for the wakeup domain (VDD3). The unused external supplies can also be shut off to conserve power. Off-mode is distinct from Full Off, where no part of the OMAP3530 is powered on.

  • VDD_MPU_IVA/VDD1:
  1. Customized scenario above – sum of power for the ARM and IVA subsystems as configured in section C.
  2. Standby1 – see figures 8 and 9.
  3. Standby2 – see figures 8 and 9.
  4. Standby3 – see figures 8 and 9.
  5. Standby4 – see figures 8 and 9.
  6. Off-mode – power during Device Off-mode.


  • VDD_CORE/VDD2:
  1. Customized scenario above – sum of power for the ARM and IVA subsystems as configured in section C.
  2. Standby1 – see figures 8 and 9.
  3. Standby2 – see figures 8 and 9.
  4. Standby3 – see figures 8 and 9.
  5. Standby4 – see figures 8 and 9.
  6. Off-mode – power during Device Off-mode.


  • VDDS_DPLL_DLL:
  1. Off, 0V – Powered off.
  2. Baseline (see details above) – power as shown in Section B.
  3. Estimated max – maximum power from simulations.
  4. Config4 (not populated) – for future use.
  5. Standby1 – see figures 8 and 9.
  6. Standby2 – see figures 8 and 9.
  7. Standby3 – see figures 8 and 9.
  8. Standby4 – see figures 8 and 9.
  9. Off-mode – power during Device Off-mode.


  • VDDS_DPLL_PER:
  1. Off, 0V – powered off.
  2. Baseline (see details above) – power as shown in Section B.
  3. Estimated max – maximum power from simulations.
  4. Config4 (not populated) – for future use.
  5. Standby1 – see figures 8 and 9.
  6. Standby2 – see figures 8 and 9.
  7. Standby3 – see figures 8 and 9.
  8. Standby4 – see figures 8 and 9.
  9. Off-mode – power during Device Off-mode.


  • VDDS_SRAM:
  1. Off, 0V – powered off.
  2. Estimated max – maximum power from simulations.
  3. Typical measured at room temp – measured power on ES3.0 silicon.
  4. Config4 (not populated) – for future use.
  5. Standby1 – see figures 8 and 9.
  6. Standby2 – see figures 8 and 9.
  7. Standby3 – see figures 8 and 9.
  8. Standby4 – see figures 8 and 9.
  9. Off-mode, 1.8V – power during Device Off-mode. This rail needs to be kept powered.


  • VDDS_WKUP_BG:
  1. Off, 0V – powered off.
  2. Estimated max – maximum power from simulations.
  3. Typical measured at room temp – measured power on ES3.0 silicon with processors at OPP3.
  4. Config4 (not populated) – for future use.
  5. Standby1 – see figures 8 and 9.
  6. Standby2 – see figures 8 and 9.
  7. Standby3 – see figures 8 and 9.
  8. Standby4 – see figures 8 and 9.
  9. Off-mode, 1.8V – power during Device Off-mode. This rail needs to be kept powered in order to keep the wake-up domain functioning.


  • VDDS:
  1. Off, 0V – powered off.
  2. Typical measured at room temp (see IOConfig1 sheet) – measured power on ES3.0 silicon with IO Pads configured as shown in “IOConfig1” sheet in the xls file.
  3. Config3 (not populated) – for future use.
  4. Estimated max – maximum power from simulations.
  5. Standby1 (room temp, optimized IO config) – see figures 8 and 9.
  6. Standby2 (room temp, optimized IO config) – see figures 8 and 9.
  7. Standby3 (room temp, optimized IO config) – see figures 8 and 9.
  8. Standby4 (room temp, optimized IO config) – see figures 8 and 9.
  9. Off-mode, 1.8V (room temp, optimized IO config) – power during Device Off-mode. This rail needs to be kept powered, but IO leakage can be minimized by selecting the appropriate internal pull-up/pull-down configuration for each IO pad in the OMAP3530.


  • VDDS_MEM:
  1. Off, 0V – powered off.
  2. Typical measured at room temp (see IOConfig1 sheet) – measured power on ES3.0 silicon with IO Pads configured as shown in “IOConfig1” sheet in the xls file.
  3. Config3 (not populated) – for future use.
  4. Estimated max – maximum power from simulations.
  5. Standby1 – see figures 8 and 9.
  6. Standby2 – see figures 8 and 9.
  7. Standby3 – see figures 8 and 9.
  8. Standby4 – see figures 8 and 9.
  9. Off-mode – power during Device Off-mode. This rail need to be kept powered for automatic ramping up of embedded LDOs for embedded memories during wakeup.


  • VDDS_MMC1:
  1. Off, 0V – powered off.
  2. 1-bit, 1.8V – measured, 1-bit mode at 1.8V.
  3. 4-bit, 1.8V – measured, 4-bit mode at 1.8V.
  4. 8-bit, 1.8V – measured, 8-bit mode at 1.8V.
  5. 1-bit, 3V – measured, 1-bit mode at 3V.
  6. 4-bit, 3V – measured, 4-bit mode at 3V.
  7. 8-bit, 3V – measured, 8-bit mode at 3V.
  8. Standby1/2/3/4 or Off-mode – see figures 8 and 9.
  9. Estimated max – maximum power from simulations.


  • VDDS_SIM:
  1. Off, 0V – powered off.
  2. 1-bit, 1.8V – measured, 1-bit mode at 1.8V.
  3. 4-bit, 1.8V – measured, 4-bit mode at 1.8V.
  4. 8-bit, 1.8V – measured, 8-bit mode at 1.8V.
  5. 1-bit, 3V – measured, 1-bit mode at 1.8V.
  6. 4-bit, 3V – measured, 4-bit mode at 1.8V.
  7. 8-bit, 3V – measured, 8-bit mode at 1.8V.
  8. Standby1/2/3/4 or Off-mode – see figures 8 and 9.
  9. Estimated max – maximum power from simulations.


  • VDDA_DAC:
  1. Off, 0V – powered off.
  2. NTSC composite – not yet measured.
  3. NTSC s-video – not yet measured.
  4. PAL composite – not yet measured.
  5. PAL s-video – not yet measured.
  6. Estimated max – maximum power from simulations.
  7. Standby1/2/3/4 or Off-mode – see figures 8 and 9.


Important Notes and Limitations[edit]

The following notes and limitations apply to Version 1.x of the OMAP3530 Power Estimation Spreadsheet:

  • Effect of temperature on static power is modeled via the ambient temperature input. A linear extrapolation is performed on measurements taken at ambient temperatures of -20°C, 25°C and 85°C.
  • Power saving effects of SmartReflex Adaptive Voltage Scaling (AVS) are not modeled. The spreadsheet is based on measurements taken on strong (also known as hot or fast) silicon without enabling AVS. Thus, the spreadsheet provides worst case power. Enabling AVS in a real application will optimize the power consumption by scaling the device operating voltage to match the silicon performance capability. AVS will result in lower actual power consumption on VDD_MPU_IVA and VDD_CORE.
  • Power-saving effects of Dynamic Power Switching (DPS) are not modeled. Baseline power assumes DPS is disabled. Again, the spreadsheet provides a worst case power estimate for a customized scenario. DPS will typically enable a real application to achieve power savings for active processing scenarios by gating clocks and power to portions of the device that are temporarily idle.
  • Only the nominal OPP3 is supported for VDD_CORE. This power rail supplies the device interconnects and peripherals.
  • The power measurements and estimates provided for the IO supply rails (VDDS and VDDS_MEM) are for the CBB package (0.4mm pitch BGA). These could vary on other packages and for different board configurations.
  • The power consumption data are based on silicon measurements supplemented with estimates.
  • It is up to the user to input reasonable utilization numbers for the MPU and IVA subsystems for the purposes of maximum power analysis. 90-100% loading on either subsystem is not realistic for most application scenarios.


References[edit]

  1. TMS320DM6446/3 Power Consumption Summary Application Report (www.ti.com Literature Number SPRAAD6A).

Revision History[edit]

Date Modification
1/16/09 Version 1.00. Initial version.
2/6/09 Version 1.01 Unlocked ARM Frequency configuration cell in spreadsheet.
2/13/09 Version 1.02 Added typical power measurements for VDDS, VDDS_MEM, VDDS_SRAM and VDDS_WKUP_BG power rails in section E.
3/12/09 Version 1.03 Updated power profile options for the ARM sub-system.
6/26/09 Version 1.05 Updated IO power measurements for standby. Added summary table for standby mode power on "StandbyModes" sheet. Fixed ARM utilization cell issue.
7/21/09 Version 1.06 Added notes for reasonable utilization on processors.
9/25/09 Version 1.07 Added OPP6 option for 720 MHz OMAP3530.
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