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OMAP35x-AM37x-DM37x with TPS65073: Design In Guide

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Abstract[edit]

This document details the design considerations of a Power Management Unit solution for the OMAP35x or AM/DM37x processors using the TPS65073 or TPS650731 device.

Introduction[edit]

The OMAP35x Applications Processors has a diverse set of power management features which potentially enable lower cost power solutions based on your application. This design-in guide describes a power solution based on the TPS65073 (or TPS650731) device. This guide can be used to evaluate this solution for your design, or help you make decisions when designing in this solution. Note that throughout this document, the term TPS65073 is used to describe the functionality in both the TPS65073 and TPS650731. When the functionality differs between the two, the text will separately mention each device.

Power Requirements and Features of OMAP35x[edit]

The following tables detail the power requirements for each OMAP35x and AM/DM37x device that is supported by a TPS65073 based power solution.

OMAP3503

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU 0.95V, 1.0V, 1.2V, 1.27V, 1.35V(*) +/- 5% 680 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 320 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 147 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 65 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset
(see Power Up sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3515

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 680 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 430 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 147 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 65 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3525

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU_IVA 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 1140 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 330 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 147 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 65 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest OMAP35x datasheet for the most current voltage values

OMAP3530

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU_IVA 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 1140 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 430 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 147 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 65 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest OMAP35x datasheet for the most current voltage values



AM3703

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU 0.95V, 1.0V, 1.2V, 1.27V, 1.35V(*) +/- 5% 740 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 230  3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 141  1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 60 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset
(see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest AM37x datasheet for the most current voltage values

AM3715

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 740 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 300 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 141 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 60 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest AM37x datasheet for the most current voltage values

DM3725

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU_IVA 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 1400 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 230 3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 141 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 60 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest DM37x datasheet for the most current voltage values

DM3730

  Power Rail Voltage Tolerance Imax (mA) Sequencing order
Core VDD_MPU_IVA 0.95V, 1.0V, 1.2V, 1.27V, 1.35V (*) +/- 5% 1400 4
Core VDD_CORE 0.95V, 1.0V, 1.15V (*) +/- 5% 300  3
I/O VDDS, VDDS_WKUP_BG,
VDDS_MEM,
VDDS_SRAM
1.8V +/- 5% 141 1
I/O VDDS_DPLL_PER,
VDDS_DPLL_DLL
1.8V +/- 5% 40 2
I/O VDDA_DAC 1.8V +/- 5% 60 After reset
I/O VDDS_MMC1,
VDDS_MMC1A
1.8V +/- 5% 22 After reset (see Power Up Sequencing for more info)
3.0V +/- 10%

Power numbers above assume SmartReflex AVS is implemented.

(*) Refer to the latest DM37x datasheet for the most current voltage values

TPS65073 Design-In Considerations[edit]

Below is a block diagram of one example of a complete power solution using the TPS65073 or TPS650731 devices to power OMAP35x or AM/DM37x. The rest of the section will detail each design consideration to tailor the power solution to your needs.

TPS65073 power solution block diagram
TPS650731 power solution block diagram


Reset[edit]

SYS_nRESPWRON rise time[edit]

The OMAP35x or AM/DM37x data sheet states that the maximum rise/fall time for SYS_nRESPWRON is 10ns.
OMAP3 with TPS65073 Design In Guide 02 1024.png
OMAP3 with TPS65073 Design In Guide 01 1024.png

In order to meet this requirement, a push-pull output buffer is required, with rise/fall time of 10ns.

The TPS65073 PGOOD output is open drain, and requires a buffer or gate with fast rise time to meet the OMAP35x requirement. If multiple reset sources are needed, you can use a AND gate as shown below to provide fast rise time for all reset sources.

OMAP3 with TPS65073 Design In Guide 06.gif

SYS_nRESPWRON timing[edit]

Typical 32KHz oscillators on the market may require up to a 1 second maximum time to stabilize. This poses a challenge in the power up sequencing in that the reset signal must be maintained low throughout this stabilization time in order to properly reset OMAP35x or AM/DM37x. The TPS65073 PGOOD output includes a 400ms delay from the time the voltage sources are stable until the PGOOD signal transitions high. The PGOOD signal depends on the sources defined PGOODMASK in TPS65073 (the default sources are DCDC1, DCDC2 and DCDC3)

If you need a further delay in your reset signal, you have two options:

  • You can use the THRESHOLD and RESET signals of the TPS65073 to double the delay time of the reset to OMAP35x or AM/DM37x. The THRESHOLD input is compared to a 1V reference. Once this threshold is met, the RESET output transitions high after a 400ms delay. Thus, with the delay of 400ms for the PGOOD output, you can create a total delay of 800ms in SYS_nRESPWRON to further extend the time needed to stabilize.
Using THRESHOLD to further extend reset signal to OMAP35x
  • You will need to add an external reset supervisor to further extend the length of the RESPWRON signal into OMAP35x or AM/DM37x. An example block diagram is below:
Using Reset Supervisor to further extend reset signal to OMAP35x

Clocks[edit]

Clock rise/fall time[edit]

OMAP35x clocks (both 32KHz and high frequency clocks) also have strict rise/fall requirements. Note the excerpts from the data manual below:

OMAP3 with TPS65073 Design In Guide 04.png

In order to meet these rise/fall times, a push-pull buffer is required to provide a faster edge on both clocks. Refer to the diagrams in the sections below.

Clock gating[edit]

When using an external oscillator for the high frequency clock, OMAP35x or AM/DM37x SYS_CLKREQ signal is used to request the high frequency clock. This signal can be used to gate the clock on power up while the processor is going through its power up sequence.

OMAP3 with TPS65073 Design In Guide 07 404.png

Generally, the 32KHz oscillator will be powered off the 1.8V supply. This should be used as a condition before applying the 32KHz to the I/Os of the processor.

32KHz clock circuit[edit]

If the 32KHz oscillator you choose exceeds the rise/fall time limit, a push-pull output buffer should be used to create a faster edge. Generally, the 32KHz oscillator will be powered off the 1.8V supply. This should be used as a gating condition before applying the 32KHz to the I/Os of the processor. Alternatively, you can use the RESET output of the TPS65073 to provide a proper gating signal for this clock.


OMAP3 with TPS65073 Design In Guide 08.gif

High Frequency Clock circuit[edit]

OMAP35x or AM/DM37x requires a high frequency clock for normal operation. OMAP35x and AM/DM37x accepts 2 different types of input clock sources:

  • a crystal can be used in combination with the internal OMAP35x oscillator for frequencies 12, 13, 16.8, or 19.2MHz.
  • a square oscillator can be used with the OMAP35x or AM/DM37x oscillator in bypass mode for frequencies 12, 13, 16.8, 19.2, 26, or 38.4MHz

When an external oscillator is used, it has strict rise/fall time restrictions of less than 2.5ns

In order to meet these requirements, a push-pull buffer is required before the clock input of the processor.

OMAP3 with TPS65073 Design In Guide 13.gif

Power Devices[edit]

TPS65073 and TPS650731 based power solutions integrate many different power sources required to power up OMAP35x devices.

The TPS65073 and TPS650731 feature the following benefits to make it an ideal PMIC for OMAP35x or AM/DM37x

  • contains 3 DCDC converters and 2 LDOs with enough supply current for all OMAP35x or AM/DM37x family devices
  • Each DCDC converter and the LDOs can be sequenced using external circuitry. The TPS650731 additionally contains circuitry to automatically sequence the power sources without external circuitry. See above block diagrams for more details
  • The second LDO inside TPS65073 can be used to power OMAP35x or AM/DM37x MMC or VDAC rail. For power sensitive applications it is recommended to power these off of a separate LDO to allow you to enable/disable the voltage separate from the PLL.
  • provides adequate default voltages on power up
  • provides I2C control of all power sources.
  • provides voltage scaling and adequate voltage granularity to allow implementation of DVFS and SmartReflex AVS.

VDAC voltage[edit]

For applications requiring VDAC voltage, a separate LDO (TPS72118) can be used which provides the proper 1.8V, 150mA maximum current. By connecting an OMAP35x GPIO, you can enable/disable this power source as the application needs it. An example schematic is below. If you are not using the video DAC on OMAP35x or AM/DM37x, you do not need to include this LDO in your design.

OMAP3 with TPS65073 Design In Guide 19 494.png

Alternatively, you can use one of the LDOs inside TPS65073 to power the VDAC.

Sleep/Standby modes[edit]

The OMAP35x and AM/DM37x have many power management features that make it attractive in power sensitive applications. One aspect of this is the sleep/standby modes, which allow the device to enter very low power states while maintaining certain levels of functionality. The OMAP35x and AM/DM37x also have the ability to go into a deep sleep mode and still recognize wakeup events when needed.

With a TPS65073 power solution, you can implement these sleep/standby modes which will allow you to take advantage of the power savings of an OMAP35x or AM/DM37x solution. Many different sleep/standby modes exist, depending on which portions need to be active for your application. With the TPS65073 solution, you have individual control over each DCDC and LDO that powers the system. These can be enabled/disabled via I2C commands. Also, the TPS65073 can vary the voltage of VDD_MPU_IVA and VDD_CORE rail to enable low power operation. Furthermore, the TPS65073 can implement OFF mode using the SYS_OFF_MODE signal. This output of OMAP35x indicates when to turn on/off the VDD_MPU_IVA and VDD_CORE rails. When input into TPS65073, SYS_MODE_OFF can control these power rails to implement low power OFF mode conditions. OMAP35x and AM/DM37x can also detect wakeup signals, and subsequently enable the TPS65073 by transitioning SYS_OFF_MODE signal.

Enabling Class 2/3 SmartReflex[edit]

The TPS65073 power solution supports both Class 2 and Class 3 SmartReflex, however, when using Class 3, you are limited to only the power features of the device. When implementing Class 3, the I2C communication is write only, so reading from the TPS65073 (necessary for touchscreen or battery charging, for example) is not possible. Class 2 SmartReflex does not have this limitation , and is fully supported along with the other features of the TPS65073.

Class 2 SmartReflex

With a Class 2 SmartReflex implementation, the ARM processor controls all of the functions of the TPS devices. You can use either OMAP35x I2C1, I2C2 or I2C3 to connect to the I2C port of the TPS65073. If possible, you should use a dedicated I2C bus between the processor and TPS65073. If you must share the bus with other peripherals, group the TPS65073 devices with peripherals which require only infrequent I2C activity. This will avoid long latencies during voltage changes. I2C communication will give you full control over both SmartReflex voltage rails (VDD_MPU_IVA and VDD_CORE) to allow power optimization on the OMAP35x.

Class 3 SmartReflex

With a Class 3 SmartReflex implementation, the SmartReflex subchip inside OMAP35x or AM/DM37x handles most of the processing and communication with the power device, so that the burden of handling voltage variations is not on the ARM processor. In this scenario, you must connect I2C4 to the TPS65073, as this I2C port will be used by the SmartReflex subchip to communicate with the TPS65073. You can configure OMAP35x or AM/DM37x with the I2C address of the TPS device, as well as the sub addresses of the appropriate registers to adjust VDD_MPU_IVA and VDD_CORE.

MMC/SD Boot[edit]

The OMAP35x or AM/DM37x processor has the ability to boot from many different sources. One possible boot configuration is to boot from MMC/SD. This configuration requires that the MMC/SD memory card is properly powered before ROM code executes (ie, on power on reset).

If MMC/SD boot is a requirement in your application, you must ensure that VDDS_MMC1 (and VDDS_MMC1A if using 8-bit MMC/SD data) is set for the proper voltage at power up. For MMC/SD cards, this is generally 3V. If your MMC/SD boot source is a managed NAND device, for example, this may only require 1.8V. In either case, ensure that the voltage source for this device is enabled on power up.

In the TPS65073 power solution block diagram, MMC voltage is connected to an external LDO. This voltage is enabled/disabled using an OMAP35x GPIO. In order to have this voltage enabled on power up, you must use an OMAP35x GPIO which defaults to an output with the correct polarity. For example, in an excerpt from the OMAP35x data manual below, the columns labeled BALL RESET STATE and BALL RESET REL. STATE are important for this functionality. BALL RESET STATE will be the state of the signal during reset (ie, during the power up sequencing). BALL RESET REL. STATE will be the state of the signal after reset is released. If you need a low enabled signal, choose a signal with 0 or L in these two columns. If you need a high enabled signal, choose a signal with 1 or H in these two columns. This will allow the external power device to be properly enabled on power up so MMC/SD boot will work. Ensure that you choose a GPIO that is not used by the ROM for booting from other sources. With a GPIO enabled power source, you can selectively enable/disable the LDO to conserve power when not using MMC/SD.

OMAP3 with TPS65073 Design In Guide 20 1024.png

Alternatively, you could use one of the LDOs that is included in the TPS65073. These LDOs will default to 1.8V only, so if you need a higher voltage on power up, you would have to choose an external LDO and use the method described above.

Software[edit]

You can find source code on the OMAP3 git tree that supports the TPS65073. Just go to the Linux OMAP kernel tree and search for "6507x". Or you can just enable the TPS65073 driver in the latest OMAP3EVM kernel by entering menuconfig and choosing Device Drivers->Voltage and Current Regulator Support->TI TPS65073 Power regulators.

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