NOTICE: The Processors Wiki will End-of-Life in December of 2020. It is recommended to download any files or other content you may need that are hosted on The site is now set to read only.

OMAP35x to AM35x Hardware Migration Guide

From Texas Instruments Wiki
Jump to: navigation, search


This document describes hardware device considerations to migrate a design based on a TI OMAP3530 Application Processor to one based on a TI AM35x System-on-Chip (Application processor). These two devices are based on similar ARM CPU cores, feature Neon & SGX graphics processor and a mixture of memory and other peripherals useful in a system environment. This document describes the details for performing this migration. Since this document describes migration from OMAP3530 device to AM35x device, familiarity with the OMAP3530 device and its documentation is assumed.

For a software migration guide, visit the OMAP35x to AM35x Software Migration Guide.

Device Architecture Comparison


Hardware Migration Overview

DDR2 support

  • New memory controller that supports DDR2.

Video capture

  • Supports 16 bit interface @ 75 MHz pclk.
  • Reduced functionality.

High End CAN Controller (HECC)


  • CPPI 3.0 compliant Ethernet MAC Controller
  • RMII support.


  • Integrated USB PHY on USB OTG port.
  • Updated USB OTG Core.

sys_clk freqency

  • Supports only 26 MHz sys_clk vs 12,19.2,26, 32 MHz on OMAP35x
  • 26 MHz crystals can be used.

32k clock generation

  • Support external 32k as well as internal generation of 32K clock based on 26 MHz clock input.

Support for 3.3 or 1.8 V I/O, vs in OMAP35x all I/O’s are 1.8 V mode only.

  • Operating IO voltage mode detection is possible via register read.

General purpose memory controller

  • 30 pf Load is supported @ 83 MHz on GPMC interface.

USB Host Port

  • Only supports precise burst mode.
  • No support for TLL mode in 3.3 V mode of operation.

Power & Clock Management support

  • No retention support.
  • Auto clock gating for VPFE, HECC, EMAC not available. For these Interfaces sw would need to gate the clocks through register configuration.
  • Single power domain for core & MPU. – simplify power sequencing requirement.
  • Single Operating point defined. No overdrive/ low power functional operating point defined.
  • No dynamic power saving by Smart-Reflex (i.e. class 2,3) supported. I2C4 instance is not available.
  • SDRC configuration will not be restored after warm reset, software would explicitly program SDRC controller after resuming from warm reset.
  • Adaptive voltage scaling(AVS), Dynamic Power saving (DPS),Dynamic voltage & Freq scaling (DVFS) not supported.

Additional Boot Mode support

  • New boot mode - EMAC boot mode supported. Please refer Initialization section of AM35x user guide for details.

Package differences

AM3517/05 is available in 2 packages:
  • ZCN -- 17x17, 0.65 mm pitch with via channel array technology
  • ZER -- 23x23, 1.00 mm pitch

Power sequencing

  • AM35x follows different power sequencing please refer device datasheet for more details