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OMAPL137, AM17x, C6747/5/3, DA83x/2x/1x/0x IO Buffer Premature Aging Assessment

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Additional content for Advisory: Digital I/O buffers age prematurely

This article applies to the following device family:

This advisory in Silicon Errata for above-mentioned devices (Silicon Revisions 2.1 and earlier), describes certain conditions wherein the device’s digital I/O buffers age prematurely. This wiki will assist the user in determining whether their device has been affected by this phenomenon, as well as help the user to implement the workarounds described in the silicon errata.

Risk Assessment

As outlined in the silicon errata, the most at-risk use cases are ones where:

1. An output buffer toggles quickly and for long periods of time. The buffer’s lifetime is inversely proportional to its switching frequency.
  • A buffer switching at 66 MHz will last about twice as long as a buffer switching at 133 MHz.
2. An output buffer operates at a voltage (DVDD) between Vnominal (3.3V) and Vmaximum (3.45V). The lower the I/O voltage, the longer the buffer will function properly.
  • A buffer with DVDD set to 3.14V will last about 3x as long as if DVDD were set to 3.3V, and about 9x as long as if DVDD were set to 3.45V.


The 3.3V digital I/O buffers on [part number] exhibit accelerated aging under use conditions with heavy switching activity, resulting in a shorter lifetime than expected. Every time a given buffer switches, it approaches the end of this lifetime; the more times a buffer toggles, the more quickly it will reach the end of its effective lifetime. For this reason, clock signals, which in most cases are toggling constantly and at relatively high frequencies, will typically be the first to display signs of this premature aging.

When an I/O buffer on this device approaches the end of its lifetime, a user will observe a degradation in output signal integrity. This is most easily observed on an output clock signal: the symptom is initially a corrupted falling edge, displaying a “ledge” or “shelf,” with increased transition time. As the aging progresses, the rising edge begins to degrade as well. Please see Figure 1 below for an example; “EMB CLK” is an affected clock signal, and “EMA CLK” is not affected but shown for comparison. At the beginning of the device’s lifetime, both signals should look the same. Note that the EMIF clocks have been disconnected from the SDRAM in the waveforms captured in Figure 1 and 2 below.

Prematurely Aged Clock
Fig.1 Clock Signal("EMB CLK") exhibiting premature aging.

In the figure above, note that:

  • The signal “EMB CLK,” which should look like the “EMA CLK” trace, is not monotonic.
  • The duty cycle for EMB CLK should be approximately 50%, but is positive for much longer than it is negative.
  • The rising edge of EMB CLK is delayed with respect to the rising edge of EMA CLK; these should in theory look the same.

As the aging progresses, both clock edges degrade severely and eventually the output signal is no longer usable as a clock. Please see Figure 2 below for an example:

Severely Aged Clock.png
Fig.2 Severely aged/degraded EMB CLK - both rising and falling edges affected.

In a typical use case, EMB_CLK (the EMIFB clock pin) will be the first signal impacted due to its high switching rate (usually between 100-133 MHz); the worst case condition with respect to switching frequency is one where the clock is constantly toggling. Because SDRAM logic is clocked based upon rising clock edges, which are initially correct even as the falling edges begin to degrade, failures may not be observed until the rising edges begin to degrade. Once the rising edges are affected, however, the user is likely to see SDRAM read/write failures as the delayed rising edges lead to timing violations.

Once the output signal integrity has begun to degrade, and failures (such as read/write errors on an SDRAM interface) have been observed, it may be possible to create passing conditions by:

1. Slowing down the output clock
2. Raising the I/O voltage
  • Note that higher I/O voltages lead to degradation. However, once the buffer is already to the point of failure, raising the I/O voltage may counteract the effect of the aging.

Neither of these two methods are suggested as workarounds, but rather as ways to diagnose the condition.

Implementing Workarounds

Addressing high switching frequency by implementing a standby mode

The basic principle for this type of workaround is that an I/O buffer should switch only as fast as necessary for required system functionality, and then only when necessary.

It is often the case in an application that there are periods of activity and periods of inactivity. For example, many consumer products receive power whenever they are plugged into a wall outlet, but are put into a type of standby mode when the customer switches the power off. During this time, there is typically some reduced level of system activity, such that the product may be turned back on with a remote control. The following are a few workarounds that can be implemented during standby mode of reduced system activity:

  • During this standby mode, the device should be powered down if possible. This way the I/O buffers do not toggle when not required to.
  • Another possibility, if complete shutdown is not an option, is to tristate any I/O buffers that do not need to be switching during standby. In the case of the EMB_CLK clocking an SDRAM device, the system software should place the SDRAM into self refresh mode, and then shut down the EMB_CLK (and the entire EMIFB bus) until the system is powered back on by the user. [reference self-refresh section in TRM?]
  • If an I/O buffer must toggle continuously, even during standby, then if possible the switching frequency should be minimized during this time of reduced activity. This may be accomplished, again, by putting the SDRAM into self refresh mode, reducing the EMIFB clock frequency, and then taking the SDRAM back out of self refresh mode. The EMIFB bus in this case would continue to function, but more slowly, thereby reducing the stress on the I/O buffer.

Lowering DVDD

As noted, reducing DVDD by 150 mV extends the buffer’s lifetime by approximately a factor of three. For this reason, it is advisable to set DVDD as low as possible. The silicon errata has reduced the minimum voltage for DVDD from 3.15V to 3.0V in order to allow the user to set their nominal DVDD as 3.15V. This is easy to implement in a system that is still in the design phase. In a system that has already been manufactured, DVDD may be lowered by:

1. If the system makes use of a programmable power management IC, modify the system firmware to set the output to a lower voltage.
2. If the system uses a voltage regulator with fixed output, replace it with another fixed regulator with lower output voltage.
3. If the system uses a voltage regulator with an adjustable output, this output voltage is usually set by a voltage divider with resistors per the regulator’s data manual. If this is the case, it is possible to change the resistor values such that the output voltage will be reduced.

Software Examples and Tools

This section is WIP and is intended to provide users with simple examples and tools that might provide assist in developing work arounds for this issue.

DISCLAIMER: The software examples provided here are simple code snippets for documented sequences/procedures in the userguides and device datasheets intended to jump start work around development. 
End user has the complete responsibilty and liability to use/test/integrate these code examples in their final end application software.
OMAPL137 EMIFB SDRAM self refresh and EMB_CLK disable example(s) is a DSP side example that shows how to put the SDRAM in self refresh mode, disable clocks to the EMIFB module and disable the EMB_CLK

OMAPL137/C674x/AM17xx/DA8xx PLL, SYSCLK, EMIF Clock Calculator

The following wiki article has a PLL calculation spreadsheet that allows you to calculate the EMB_CLK frequency based on various clock inputs and CPU/SYSCLK/PLLM combinations.

Safely Modifying the EMIFB frequency in application

SDRAM_PLL_freq_change_test Sample code is a DSP side example created using non-OS code that shows how to safely reduce or increase the EMIFB frequency in the application. The application runs from the L3 memory and does a memory read-write test to the SDRAM after each frequency switch. In an OS environment, it is recommended to disable all tasks/threads and EDMA transfers to stop access to the SDRAM before the starting the EMIFB frequency switching sequence.

Frequently Asked Questions

 Is TMS320C6748/6/2 DSPs, OMAP-L138/2 DSP + ARM9 processors, Sitara™ AM18x ARM9™ processor family impacted as they are very similar designs?

Answer: No. It has been confirmed that the impact is limited to TMS320C6747/5/3 DSPs, OMAP-L137 DSP + ARM9 processors, Sitara™ AM17x ARM9™ processors and DA83x/82x/81x/80x devices. Although the designs are thought to be similar to TMS320C6748/6/2 DSPs, OMAP-L138/2 DSP + ARM9 processors, Sitara™ AM18x ARM9™ processors , the I/O buffers used in the device designs are different.  It is NOT the same I/O buffer used in the affected devices; therefore this problem does not impact theTMS320C6748/6/2 DSPs, OMAP-L138/2 DSP + ARM9 processors, Sitara™ AM18x ARM9™ family of processors.

Are other devices affected by this risk besides those listed above?

Answer: No. We have completed audits of all IO’s on all Embedded Processing devices and only those listed under this wiki are affected.

Are all I/O’s of the affected devices at risk of this premature aging mechanism?

Answer: Yes all 3.3V IO’s on the affected devices are at risk of this premature aging mechanism.Slower speed interfaces will have a longer lifetime before causing system fails due to system timing margins and slower toggle rates. We therefore expect the EMIF clock buffer I/O to be the highest risk in many applications.

Are inputs affected by this premature aging mechanism?

Answer: Input buffers or Input stage of IO’s are not affected by this premature aging mechanism. Only the output stage has this issue.