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StarterWare EMAC

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Introduction[edit]

The Ethernet Media Access Controller (EMAC) and Management Data Input/Output (MDIO) peripherals on AM1808 provide a full-featured Ethernet interface. The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The EMAC module provides an efficient interface between the processor and a local network. The EMAC on AM1808 supports 10Base-T (10 Mbits/sec) and 100BaseTX (100 Mbits/sec), in half-duplex and full-duplex modes. The EMAC control module provides an interface from the CPU to the EMAC and MDIO modules. The EMAC control module controls device interrupts and incorporates an 8k-byte internal RAM to hold EMAC buffer descriptors (also known as CPPI RAM). The MDIO module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHYs connected to the device by using a shared two-wire bus. Applications can use the MDIO module to configure the auto negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The StarterWare APIs for configuring and using EMAC and MDIO are listed in include/emac.h and include/mdio.h, respectively.

Programming Sequence[edit]

The device is powers on with EMAC in a disabled state. Proper pin multiplexing must be applied for the EMAC and MDIO modules. Also, before initializing EMAC, the EMAC and MDIO modules must be powered on using the PSC registers. The following sequence can be used to configure and operate the EMAC and MDIO modules.

  • Enable pin multiplexing for EMAC and MDIO using the EMACPinMuxSetup() API.
  • Enable the EMAC and MDIO modules in the PSC registers using the PSCModuleControl() API.
  • Initialize the EMAC module by calling EMACInit(). This API resets the EMAC and EMAC Control Module Registers.
  • Initialize the MDIO Module using MDIOInit(). Insert a short delay after this function returns to ensure that MDIO module initialization completes successfully before using other MDIO APIs.
  • Auto negotiate with the PHY device connected to MDIO. PHY Auto negotiation APIs are provided for this purpose.
  • After completing auto negotiation, get the auto negotiation result using the respective PHY’s link partner ability API and set the duplex mode of operation in the EMAC using EMACDuplexSet().
  • Set the MAC Address in the EMAC hardware using EMACMACAddrSet().
  • Enable unicast for a specific channel using the EMACRxUnicastSet() API (optional).
  • Initialize the TX and RX buffer descriptors in the CPPI RAM, which is local to the EMAC.
  • Enable the TX operation in EMAC using EMACTxEnable(). This enables the EMAC hardware transmit operation. However, transmission will not start until a valid descriptor pointer is written using EMACTxHdrDescPtrWrite().
  • Enable the RX operation in EMAC using EMACRXEnable().
  • Write the RX Header Descriptor Pointer using EMACRxHdrDescPtrWrite(). The EMAC hardware will start receiving data at this point. The data will be stored to the buffer pointer in this buffer descriptor. After the buffer corresponding to this descriptor is filled, the next descriptor is used by the EMAC hardware according to the buffer descriptor settings.
  • Enable MII using EMACMIIEnable().
  • Enable the Transmit and Receive Pulse interrupts using EMACTxIntPulseEnable() and EMACRxIntPulseEnable(). The interrupts will be routed through the EMAC Control Core to the CPU interrupt controller. This enables the EMAC TX and RX pulse interrupts at EMAC peripheral level only. The core interrupts must be enabled separately in the interrupt controller.

The following guidelines should be observed when writing an EMAC interrupt service routine (ISR):

  • In an EMAC Transmit ISR, the interrupt must be acknowledged to the EMAC hardware using EMACCoreIntAck(). However, the interrupt will be cleared only if the completion pointer is written using the EMACTxCPWrite() API with the last processed TX buffer descriptor.
  • In an EMAC Receive ISR, the interrupt must be acknowledged to the EMAC hardware using EMACCoreIntAck(). Again, the interrupt will be cleared only if the completion pointer is written using the EMACRxCPWrite() API with the last processed RX buffer descriptor.
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