NOTICE: The Processors Wiki will End-of-Life in December of 2020. It is recommended to download any files or other content you may need that are hosted on processors.wiki.ti.com. The site is now set to read only.

SystemAnalyzerTutorial7

From Texas Instruments Wiki
Jump to: navigation, search

Tutorial 7: Using UIA and System Analyzer with OpenMP projects

UNDER CONSTRUCTION!

Background Info

References

OpenMP program code is typically constructed as a single image that is loaded into shared memory and executed by all cores, with each core maintaining its own state in its own local memory. For the Keystone Architecture devices (e.g. the C6678), the program code is typically loaded into the MSMC (multicore shared memory controller) SRAM and the local data is stored in L2SRAM.


An OpenMP Example Project

Prerequisites (tested configuration)

  • XDC 3.23.4.60
  • IPC 1.24.3.32
  • OMP 1.1.3.2
  • Sys/BIOS 6.33.6.50
  • MCSDK PDK TMS320C6678 1.1.2.5

Building the project

  • in the Project Explorer view, right click on the project and select Build Configurations / Set Active / Release)
  • Configure the build settings
  • In the Project Explorer view, right click on the project and select "Show Build Settings...".
  • Click on General in the left pane, and ensure that the compiler version is TI v7.4.0
  • Click on the RTSC tab and ensure that you have the correct XDC version, the correct package versions selected and the correct Platform selected (e.g. ti.omp.examples.platforms.evm6678)
  • Click OK to close the Build Options dialog
  • Build the project.

Launching the Project

The basic approach to launching this type of program is to

  • load the program into core 0 (the master core)
  • load symbols into all other cores (the slave cores) and restart the cpus (so that the PC is at c_int00)
  • run to main on core 0. This will initialize the shared memory region used for IPC with all other cores. Core 0 will then wait for all of the other cores to start up.
  • run all of the other cores. When core 0 detects that all cores are running, it will hit main and stop.
  • manually halt all the other cores
  • Start System Analyzer->Live to capture events
  • run CPU 0 and then the other cores

When working with this type of program in CCS, it is important to avoid the use of software breakpoints. The way that software breakpoints work is that a special ‘software breakpoint’ opcode is written into memory by CCS and, when the CPU executes this breakpoint opcode, the debugger is notified. The debugger then replaces the breakpoint opcode with the original program opcode that was located at that address and updates the Debug View. If your program is located in shared memory, this causes problems. The debugger will restore the original opcode when the first CPU hits the breakpoint, so all of the other CPUs will not see the breakpoint at all.

Target Configuration

CPU 0 (and only CPU 0) should be configured to run the EVM board's gel file as the initialization script. To configure this:

  • Open the Target Configuration view (Views / Target Configurations)
  • Open your evm board's .ccxml file in the editor by double-clicking on it in the target configuration view
  • Open the Advanced tab
  • Expand the tree so that C66xx_0 is selected
  • Click on the Browse button to the right of the initialization script text box
  • Browse to the gel file for your EVM board
  • e.g. for the C6678 EVM, browse to ccsv5\ccs_base\emulation\boards\evmc6678l\gel in your CCS install folder and select the evmc6678l.gel file
  • Tutorial7 TargetConfiguration.gif

For the Slave cores (CPU 1-7)

  • Download the attached File:Clear stale state.zip file and unzip the gel file it contains into e.g. c:\ti or some other convenient folder.
  • In the .ccxml file editor's advanced tab, select each of the slave cores (C66xx_1, etc.) and configure the initialization script text box with the path to the downloaded clear_stale_state.gel file.

Save the file (File / Save)


Launch Configuration

Many of the steps required to launch an OpenMP project can be automated by creating a custom launch configuration. For instructions on how to configure the launch in the version of CCS that you are using, please click on the appropriate link below:

At this point, you should have the program loaded and running, and System Analyzer should be collecting events.

Events should be displayed in the System Analyzer Live Session: Logs view. If the warning "Warning: Waiting UIA SyncPoint data" is always displayed in the Live Session: Logs view status bar, you can skip the sync points by right clicking on the view and selecting Live Session / Skip Sync Points for Correlation.

  • Once the program has finished the OpenMP program code, one of the last events you should see displayed in the Live Session Logs view should be an event that has a message text of "Stop:OMP PARALLEL FOR, using 8 cores"
  • To see a table comparing the processing times for the parallel sections in the program, in the Live Session: Logs view toolbar click on the word "Analyze" and select Duration. The Duration Configuration dialog box will be displayed - click Start. In the Duration view, click on the AutoFit Columns button Tutorial7 autofit.gif. You should see a table that looks something like the one below:

Tutorial7 Duration 8cores.gif


IMPORTANT

  • Once you have run the program, the safest way to reload it is to terminate the current debug session and to re-launch it. There are a number of bugs in CCSv5.3 relating to the way groups behave and to the use of real-time mode to upload events that can cause problems, and terminating the session avoids these. (These bugs have been fixed in CCSv5.4).

Links