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TI814x-DDR3-Init-U-Boot Wordwise SWleveling

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ReadMe First

The purpose of this document is to describe how to initialize DDR3 on TI814x using software leveling. This approach uses static values for the software leveling process.


  1. Excel spreadsheet for obtaining the seed values which is the input to the CCS based app File:RatioSeed
  2. CCS based program DDR3_slave_ratio_search_TI814x.out File:DDR3 slave ratio search
  3. TI814x U-Boot source code based on PSP release
  4. U-Boot-DDR3_TI814x.patch File:U-Boot-DDR3 TI814x.patch (Only if you are using u-boot release
  5. TI814X GEL File File:Ti814x
  6. Asymmetric-DDR3-memory-inteface.patch File:Ti8148 asymmetric ddr inteface.patch for adding support for Asymmetric DDR memory interface against release
  7. U-Boot User Guide which is a part of the PSP release
  8. CCS 5.1 or above installed on Windows XP with Service Pack 2
  9. Details of CCS 5.1 installation guidelines are given in

Download all the required file to the PC before proceeding to the next step.


In order to correctly setup DDR3 in TI814x devices the approach used is software (slave ratio) leveling. The values to be used for software leveling are for specific board type and needs to be estimated using the CCS based program DDR3_slave_ratio_search_auto.out The program searches the window for the following Slave Ratio values on board based on the initial seed values to be keyed in on the command line(calculated based on DDR2/3 board topology), as explained in the next section.

  1. Read DQS Slave Ratio
  2. Read DQS Gate Slave Ratio
  3. Write DQS Slave Ratio

Note that this program needs to be run for each new board type and for each operating frequency of DDR3.

Obtaining the seed values

The seed values for the ratios may be obtained using the File:RatioSeed spreadsheet. The spreadsheet takes the following as inputs:

Excel screen.JPG

1. DDR3 clock frequency

2. CK and DQS trace lengths in inches for each of the byte lanes.

The user inputs should be on these cells that are marked green. Once these fields are input, feed the values for B17, B18 and B19 for respective parameters to the CCS program.

Hardware and CCS Setup


You can skip this step if CCS is already configured. Make sure the settings are as mentioned in the configure step.

  • Connect the JTAG emulator to the TI814x using the JTAG ribbon cable and the 20/14 pin JTAG adapter (board specific).
  • Make sure the Boot Mode / Configuration Select Switch are set to all 0s.
  • System Requirements – CCS 5.1 or above installed on Windows XP with Service Pack 2
  • Start CCSv5.1 by navigating to 'Start' menu in Windows XP
  • Select the workspace folder where you want to store your project
  • Use target configuration file ti814x.ccxml. If there is a need to crate a new configuration, then follow steps below
    • Select new Target Configuration "View -> Target Configurations",Right click on "User Defined" folder then New Target Configurations
    • Connection = TI XDS560 Emulator
    • Board or Device = TI814xEVM (On some CCS versions you might have to use the internal name of TI814x or Centaurus for this)
    • Save configuration, e.g., ti814x.ccxml
    • From next run, the project and target configuration will be readily available and can be skipped
  • Select "Debug Perspective" in CCS if it is not there already: Window -> Open Perspective -> Debug
  • Select View -> Target Configurations. Look for the target configuration ti814x.ccxml created in the previous step
  • Right click and click "Launch Selected Configuration" this should launch debug session
  • In Debug view select "TI XDS560 Emulator_0/Cortex A8" connection.
  • Right click and select "Set Debug Scope" option. This will make remove all the cores except Cortex A8 from the debug view.
  • Right click on the Cortex A8 core listed and click on "Connect Target"
  • A "Disassembly" view with PC halted should pop up in one of the tabs. If not, issue a 'System Reset' from Run menu and then click on Halt

Generating the static values

Loading GEL File

  • Ensure that the GEL file File:Ti814x is copied to the Windows Machine
  • Select Tools -> GEL Files in CCS
  • This opens a new tab in the Debug view. On right hand side empty area in this window, right click and use "Load GEL"
  • Navigate to the directory containing gel file and select Ti814x ddr3.gel
  • A "Scripts" menu item (on top) should now be available
  • Select Script -> TI814x DDR Configuration -> DDR3_EMIF0_EMIF1_400MHz_Config
  • This will perform DDR3 initialization.
  • On success, you should see following at the CCS console:
CortxA8: GEL Output: 	DM814x DDR DPLL CLKOUT  value is  = 400  
CortxA8: GEL Output: 	DM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress.........  
CortxA8: GEL Output: 	DM814x DDR,DMM PRCM configuration is Done  
CortxA8: GEL Output: 	DM814x DDR PHY Configuration is Done  
CortxA8: GEL Output: 	DM814x DDR IO Control Configuration is Done  
CortxA8: GEL Output: 	DM814x VTP Configuration is Done  
CortxA8: GEL Output: 	DM814x DMM LISA register Configuration is Done 
CortxA8: GEL Output: 	DM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. 
  • Note that sometimes the Scripts menu is disabled. In this case, go to Debug window and select "TI XDS560 Emulator_0/CortexA8 (top level node) and the Scripts menu should get activated.

Loading the CCS app

  • At this point, A8 in in user(USR) mode (marked as USR in the bottom right corner of CCS Status Bar). It needs to be in Supervisor(SPV) mode to run U-Boot and the Linux Kernel. Follow these steps:
  1. Goto menu View -> Registers
  2. Expand CPSR
  3. Select “M” and set it to 0x13
  4. These steps set the CPSR.M to 0x13 (SPV mode).
  5. Goto Tools -> ARM Advanced Features select NEON Enabled
  • Select Run -> Load -> Load Program. Select the CCS program DDR3_slave_ratio_search_TI814x.out for loading.

Running the app


Enter 0 for DDR Controller 0 & 1 for DDR Controller 1 

DDR START ADDR=0x80000000 

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window

Enter the input file Name 

The Slave Ratio Search Program Values are 
Read DQS		6a 	5 	37 	65
Read DQS GATE	168	60 	e4 	108
Write DQS		87 	0 	43 	87
Write DATA	ad 	4b 	7c 	62
===== END OF TEST =====   

In the above example the seed values calculated based on the DDR3 board topology are entered.

Based on the seed value, the search window may or may not converge for the the slave ratios listed in Overview section.

Note : In the above example the output result gets saved in "Ti814x_Ratio_values.txt" file.

The calculated compensation values are assumed to apply to both EMIF0 and EMIF1. However if trace lengths differ significantly between EMIF0 and EMIF1 on customers board, they may have to supply separate values for EMIF0 and EMIF1.

For Asymmetric DDR2/3 memory interface(Where trace lengths of DDR0 & DDR1 for CK & DQS are different), then DDR3_slave_ratio_search.out should be run twice to calculate the Slave Ratio values for DDR0(Memory Map Address =0x8000_0000) & DDR1(Memory Map Address).

For Symmetric DDR2/3 memory interface(Where trace lenghts of DDR0 & DDR1 for CK & DQS are almost equal or exactly equal) , then can be run for DDR0 interface only to calculate the Slave ratio values and use same slave ratio values for DDR1 interface also.

You may choose to run it one more times to be sure that the converged "optimum values" are same. However, there can be small variations across different run based on the voltage and temperature on the board. In that case you can choose to enter converged values from any one of the run.

Reset the Board or Issue POR. Repeat the steps for searching for the slave ratios for different DDR3 frequencies.

Modifying U-Boot

The values generated in the previous step are used in U-Boot (with the File:U-Boot-DDR3 TI814x.patch patch applied {Only if you are using u-boot release or older}) for the software leveling process. While plugging in the values in U-Boot please ensure that the changes are done for the same clock speed for which the program was executed in the previous step.

  • Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h or ddr_defs.h for and older release versions.

The values obtained in the previous step need to be plugged under the TI814X appropriate #define in the order emif0 : emif 1

/* TI814X DDR3 PHY CFG parameters   <emif0 : emif 1> */
#define DDR3_PHY_RD_DQS_CS0_DEFINE              ((phy_num == 0) ? 0x3a : 0x3a)
#define DDR3_PHY_WR_DQS_CS0_DEFINE              ((phy_num == 0) ? 0x22 : 0x22)
#define DDR3_PHY_RD_DQS_GATE_CS0_DEFINE         ((phy_num == 0) ? 0xe6 : 0xe6)
#define DDR3_PHY_WR_DATA_CS0_DEFINE             ((phy_num == 0) ? 0x42 : 0x42)

Note that the values used here are for representative purposes only. Use the values obtained from the CCS program over here

  • Open the file include/configs/ti8148_evm.h and make sure the following changes are there
#define CONFIG_TI814X_EVM_DDR3                  /* Configure DDR3 in U-Boot */
//#define CONFIG_TI814X_EVM_DDR2                /* Configure DDR2 in U-Boot */

Register to U-Boot Macro Definition Mapping Table

Register Name Constant Name
SDRRCR2 Not Used N/A
PMCR Not Used N/A
PBBPR Not Used N/A
  • Rebuild and flash U-Boot as described in the U-Boot user guide.


Q. How to enable single EMIF configurations on TI8148 u-boot ?

Ans: To enable single EMIFconfiguration we have to apply the patch file File:Ti8148 single emif and change the values of the macro USE_EMIF1 to 0 in the "arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h"

This patch disables the configurations for the 2nd EMIF instance in the evm file and also it uses a minimal non-interleaved LISA_MAP configurations.