Please note as of Wednesday, August 15th, 2018 this wiki has been set to read only. If you are a TI Employee and require Edit ability please contact x0211426 from the company directory.
Wait in Reset
- Wait-In-Reset has the processor under debugger control from the first instruction the processor executes. This allows the user to step or run the processor through the first instructions that it executes. This is very useful for debugging software such as boot code, or initialization code.
- Wait-In-Reset mode is usually detected based on the state of the EMU0 and EMU1 pins at power up and can be latched on power-on reset. For some devices, Wait-In-Reset mode is implemented by the ICEPICK module.
- For some devices, if the card utilizes the proper JTAG Connectors with the system reset signal under debug control, wait in reset can be done by the debugger.
- Some ARM based chips are designed to implement a similar mechanism without EMU0/EMU1 support. The mechanism involves setting on-chip vector catch hardware to provide a breakpoint on processor reset, then issuing the reset and handling that breakpoint. This may not work for initial power-up in all cores.