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# Overview

Modern mobile computing devices use hardware and software power management techniques to control power consumption and thereby extend battery life.

This document provides a high level overview of Power Management capabilities of Windows CE6, the TI ARM_A8 (OMAP35xx/DM37xx/AM35xx) processor family, and BSP for these processors.

A detailed discussion of power management is beyond the scope of this document and the reader is encouraged to consult the Windows CE6 documentation and the TI ARM_A8 processor family documentation for more information.

# Windows CE Power Management Software

This section discusses, in generic terms, the power management capabilities of Windows CE6. See the Windows CE6 documentation for more information.

CPU Idle State: When the kernel scheduler is idle (no threads are ready to run) the kernel will activate BSP code that places the CPU into a reduced power state until an interrupt occurs. This may happen many times in any given second and is transparent to application and driver behavior.

Power Manager Model: TI WinCE BSP for OMAP35xx/DM37xx and AM351xx CE6 use the Power Manager model for power management rather than the add-hock methods (GWES timers, backlight timers, etc.) supported in earlier versions of Windows CE. Note that because Windows CE6 still includes vestiges of these add-hock methods, some of the documentation, control panel applications and registry entries are irrelevant or incorrect.

D States (Power States): Windows CE includes a power management subsystem that (by default) supports 5 power states from D0 (full on) to D4 (full off). Device drivers can register to receive notifications of changes to the system power state. Device drivers also have individual power states and can interact with each other to manage power state relationships.

Suspend/Resume: The Windows CE power management subsystem supports suspending the system by placing the GWES, the device drivers, and the file system manager into the D4 state. The OAL will then continue the suspend process by saving critical processor registers, placing the CPU into a low power state to await a wake up event. After a wake up event, the process will be reversed by the resume sequence. Note that the actual suspend power state of each of the device drivers is determined by the device driver design, most will use D4 but devices that can wake the system from suspend may use D3. The Ethernet driver is an example of a driver that uses D3 for suspend.

Idle Timers: The Graphical Windowing Event Systems (GWES) works with the Power Manager (PM) to control idle timers based on user and system activity detection that can be configured to change the system wide power state. These timers are configured using registry entries.

User Idle Timer: When the user interface is idle for a period of time (configurable using registry entries), PM can change the system power state to D1. Device drivers that receive notification of system power state changes can then respond by going to a reduced power state as applicable. An example of a device driver that can be configured to respond to the D1 system power state is the backlight driver.

System Idle Timer: When the system appears to be idle for a period of time (configurable using registry entries), PM can change the system power state to D2. Device drivers that receive notification of system power state changes can then respond by going to a reduced power state as applicable. An example of a device driver that can be configured to respond to the D2 system power state is the backlight driver.

System Suspend Timer: When the system appears to be idle for an extended period of time (configurable using registry entries), PM can change the system power state to D4 causing the system to suspend.

The default association of power states to system states:

 D0 Full On D1 User Idle D2 System Idle D3 Off/Suspend with wake capability D4 Off/Suspend

# Power Management Support in TI ARM_A8 processor

This section discusses, in generic terms, the power management capabilities of the TI ARM_A8 processor family. See the processor documentation for more information.

Controller Interface Clock Management: The interface clocks are used to access the registers in on-chip subsystems. To save power, interface clocks can be disabled when the registers in a subsystem are not being accessed.

Controller Functional Clock Management: The functional clocks are used to run the logic in on-chip subsystems. To save power, functional clocks can be disabled for subsystems that are not being used.

Shared Clock Management: The clock sources that are shared between several subsystems can be disabled when none of the subsystems that use the clock are being used.

Power Domain Management: There are several power domains inside the TI ARM_A8 processor family. The power supplies to these domains can are switched on/off according to the PRCM subsystem register configuration and rules built into the processor logic design. This allows the power supply to sections of the procesor chip to be shut off when not in use or when the system enters a low power state (such as during suspend).

Programmable Clock Speeds: Clocks for many on-chip subsystems can be programmed to run at different frequencies. The MPU (CPU), IVA (DSP) and core functional clocks are the most important variable speed clocks for power management. The maximum clock frequency that can be used for these blocks depend on the chip manufacturing test results (speed grade) and on the voltage being supplied to the domain that the subsystem is part of.

Programmable Domain Voltages: The TI ARM_A8 voltage processor can communicate with an external PMIC (Power Management Integrated Circuit) to control the voltage supplied to the processor power domains. For some domains, the domain voltage can be reduced if the functional clocks to subsystems within that domain are running at a reduced frequency. Voltage changes are important because the power consumption used by logic circuits is roughly proportional to the square of the voltage used to power the logic times the clock rate (Power = Voltage2 * Frequency). Valid voltage and frequency pairs are called operating points (OPP).

Smart Reflex Data: During factory chip testing, information about the clock and voltage requirements for some subsystems is collected and written to write once memory on the chip. This information can be used to fine tune the operating points for the MPU/IVA and CORE domains. This feature is available for DM37xx chip, however the DM37xx chip may not have clock and voltage information written in the chip.

Note: AM3517/05 doesn't support separate processor and core voltage domain and only has single core voltage domain VDD_CORE fixed
in 1.2 V. The max processor clock frequency is derived from DPLL1 and can be reduced by the procedure described in TRM.However the
VDD_CORE voltage needs to be kept at 1.2 V. The core clock frequency derived from DPLL3 can not be changed.
Smart Reflex is also not supported in AM35xx. 

# BSP Power Management Software

## Overview

This section discusses the power management capabilities for the following Windows CE6 BSP (Board Support Package):

• EVM_OMAP3530 BSP for OMAP35xx/DM3730 EVM
• AM35x_BSP for AM35xx EVM

Controller Interface Clock Management: Many devices drivers that are associated with a controller inside the TI ARM_A8 processor disable interface clocks for the controller when not accessing the registers.

Controller Functional Clock Management: Many devices drivers that are associated with a controller inside the TI ARM_A8 processor disable functional clocks for the controller when the controller is not being used.

PRCM Clock Management: The PRCM manager understands the relationships between clocks and maintains a reference count for each clock resource (interface clocks, functional clocks, shared clocks) to allow a shared clock to be shut off when all of the controllers that use the clock are shut down.

PRCM DPLL Management: The PRCM manager allows the frequency of some of the DPLL (Digital Phase Locked Loop) clock generators to be adjusted.

PRCM Domain Management: The PRCM manager understands the relationships between voltage domains and clock domains and tracks reference counts for domains to allow unused domains to be powered off.

## Operating Point (OPP)

The MPU and IVA (CPU and DSP) domains share the same power supply (VDD1) and are managed together. Example operating points (OPPn) are shown below. See the BSP inc\bsp_opp_map.h file for details about the currently supported OPPs. The maximum OPP that the processor can support depends on the chip version and grade. Note that if the Smart Reflex management is active, the actual voltages used may be altered according to the SmartReflex data provided by the processor chip.

Note that AM3517/05 does not support multiple Operating Mode. However, it is possible to use a lower processor frequency by the procedure shown in section 4.11.5.1.4 Processor Clock Control in the AM3517 TRM.

OMAP35xx Processor Family:

MPU/IVA OPPs:
OPP1: VDD1 = 0.975 V, MPU = 125 MHz, IVA = 90 MHz
OPP2: VDD1 = 1.000 V, MPU = 250 MHz, IVA = 180 MHz
OPP3: VDD1 = 1.200 V, MPU = 500 MHz, IVA = 360 MHz
OPP4: VDD1 = 1.275 V, MPU = 550 MHz, IVA = 400 MHz
OPP5: VDD1 = 1.350 V, MPU = 600 MHz, IVA = 430 MHz
OPP6: VDD1 = 1.350 V, MPU = 720 MHz, IVA = 520 MHz
CORE OPPs:
OPP1: VDD2 = 1.050 V, CORE = 166 MHz
OPP2: VDD2 = 1.150 V, CORE = 332 MHz

DM37xx Processor Family:

MPU/IVA OPPs:
OPP1: VDD1 = 0.935 V, MPU = 300 MHz,  IVA = 260 MHz
OPP2: VDD1 = 1.100 V, MPU = 600 MHz,  IVA = 520 MHz
OPP3: VDD1 = 1.260 V, MPU = 800 MHz,  IVA = 660 MHz
OPP4: VDD1 = 1.310 V, MPU = 1000 MHz, IVA = 800 MHz
CORE OPPs:
OPP1: VDD2 = 1.050 V, CORE = 200 MHz
OPP2: VDD2 = 1.150 V, CORE = 400 MHz

Operating Mode Description: The operating points of the MPU/IVA and CORE are managed together as the OPM (Operating Mode) of the chip. Example operating points (OPMn) are shown below.

OPM0: MPU/IVA OPP1, CORE OPP1
OPM1: MPU/IVA OPP1, CORE OPP2
OPM2: MPU/IVA OPP2, CORE OPP2
OPM3: MPU/IVA OPP3, CORE OPP2 (default for DM37xx)
OPM4: MPU/IVA OPP4, CORE OPP2
OPM5: MPU/IVA OPP5, CORE OPP2 (default for OMAP35xx)
OPM6: MPU/IVA OPP6, CORE OPP2

Operating Mode Control: The bootloader sets a default operating mode using the BSP_OPM_SELECT_35XX and BSP_OPM_SELECT_37XX variable set in the BSP configuration batch file. Note that if the power management software (below) is enabled then the initial operating mode used by the OS may be different from what set by the bootloader, and may even vary based on system activity.

## Dynamic Voltage and Frequency Scaling (DVFS)

Allows the operating mode (see above) to be changed while the system is operating. Domains controlled by this system are the CORE and the MPU/IVA (CPU/DSP) domains. The OMAP35xx/DM37xx PRCM subsystem is used to send commands to the external PMIC to control the domain voltages and the PRCM DPLL management capability is used to change the domain frequency.

This feature is enabled by selecting the following catalog item:

• Third Party \ BSP \ EVM_OMAP3530:ARMV4I \ Drivers \ PM \ Constraint Adapter \ DVFS

The following is the sample settings for CPU Load Policy in omap_pm.reg:

[HKEY_LOCAL_MACHINE\OMAPPMX\Constraints\DVFS\35xx]
"OpmInit"=dword:5                           ;kOpm5
"OpmFloor"=dword:0                          ;kOpm0
"OpmCeiling"=dword:5                        ;kOpm5
;MPU1Map lists the MPU/IVA OPP associated with each OPM (0..6)
;MPU (VDD1) kOpp values for each kOpm value (kOpm0, kOpm1, ..., kOpm6) see inc\bsp_opp_map.h
;Each MPU kOpp value represents a VDD1 voltage, MPU DPLL1 frequency and IVA2 (DSP) DPLL2 frequency triple used fo each kOpm
"MPU1Map"=multi_sz:"0","0","1","2","3","4","5"
;CORE1Map lists the CORE OPP associated with each OPM (0..6)
;CORE (VDD2) kOpp values for each kOpm value (kOpm0, kOpm1, ..., kOpm6) see inc\bsp_opp_map.h
;Each CORE kOpp value represents a VDD2 voltage and CORE DPLL3 frequency pair used for each kOpm
"CORE1Map"=multi_sz:"0","1","1","1","1","1","1"


This power policy subsystem is configurable using registry entries and uses information about the CPU load (ratio of time the CPU spends running code as opposed to being in the CPU Idle State) to select a DVFS state for the CORE and MPU/IVA domains. This driver requires the DVFS driver.

This feature is enabled by selecting the following catalog item:

• Third Party \ BSP \ EVM_OMAP3530:ARMV4I \ Drivers \ PM \ Policy Adapter \ CPU Load Policy<br>

The following is the sample settings for CPU Load Policy in omap_pm.reg:

[HKEY_LOCAL_MACHINE\OMAPPMX\Policies\CPULOAD\35xx]
"CeilingOpm"=dword:5
"FloorOpm"=dword:0
;"NominalOpm"=dword:3
"BootOpm"=dword:5
; OpmFrequency has one entry per operating mode (kOpm0..kOpm9), uppercase hex values
"OpmFrequency"=multi_sz:"7D","7D","FA","1F4","226","258","2D0","0","0","0"
;"OpmFrequency"=multi_sz:"125","125","250","500","550","600","720","0","0","0" ;in decimal for reference
; OpmThreshold has one entry per operating mode (kOpm0..kOpm9), uppercase hex values
"OpmThreshold"=multi_sz:"46","64","D2","1A9","20D","23F","2A3","0","0","0"
;"OpmThreshold"=multi_sz:"70","100","210","425","525","575","675","0","0","0"  ;in decimal for reference


## Device Monitor Policy Management (DEVMON)

This power policy subsystem listens for device state changes and tries to ensure that the OPM (Operating Mode) stays high enough for the active devices to operate correctly. This driver requires the DVFS driver. Note that this driver also controls the lowest suspend state that the chip can enter during suspend.

The following is the sample settings for CPU Load Policy in omap_pm.reg:

 [HKEY_LOCAL_MACHINE\OMAPPMX\Policies\DEVMON]
;LATENCY_STATE_CHIP_OFF 0, CORE+MPU+OTHER = OFF",
;LATENCY_STATE_CHIP_OSWR 1, CORE+OTHER = OSWR, MPU = CSWR",
;LATENCY_STATE_CHIP_CSWR 2, CORE+OTHER = CSWR, MPU = CSWR",
;LATENCY_STATE_CORE_CSWR 3, OTHER=OFF/OSWR/CSWR/INACTIVE, CORE = CSWR, MPU=CSWR",
;LATENCY_STATE_CORE_INACTIVE 4, OTHER=OFF/OSWR/CSWR/INACTIVE, CORE = INACTIVE, MPU=CSWR",
;LATENCY_STATE_MPU_INACTIVE  5, OTHER=OFF/OSWR/CSWR/INACTIVE, CORE+MPU = INACTIVE"
; CSWR = Clock Stopped With Retention
; OSWR = Off State With Retention
"SuspendState"=dword:0



Note that the actual state entered by the CPU during suspend may be higher than the "SuspendState" due to hardware or software constraints. If DEVMON is not enabled, then the suspend state is controlled by the initial value of the _suspendState variable in src\oal\oallib\oem_latency.c.

DEVMON uses common_ti_v1\omap3530\pm\policyadapters\devmon\devoppmap.h information to set the minimum OPM allowed when a device is active. The default values in this file constrain the minimum OPM to OPM1 when any of the MCBSPn device clocks are active and to OPM2 when any of the USB device clocks are active. Note that reducing the minimum OPM values for these devices may reduce power consumption for systems that do not use or can tolerate some reduction in performance for the MCBSPn and USB devices.

## Interrupt Latency Constraint Management

Places constraints on the DVFS operating mode and the state used when the CPU Idle State is entered. This system uses information about unmasked interrupts and the maximum interrupt latency that each interrupt can tolerate to prevent the CPU from being placed into a state where interrupt latency times are too high for proper operation of the device associated with the interrupt. The configuration of this feature is fixed in the OAL (no configuration options). This feature is part of DVFS.

This feature is enabled by selecting the following catalog item:

• Third Party \ BSP \ EVM_OMAP3530:ARMV4I \ Drivers \ PM \ Constraint Adapter \ INTR LATENCY

## System State Policy Manager

Provides constraints on the DVFS operating mode based on user activity (see Platform Builder help for more information by searching for "UserIdle").

This feature can be enable by select the following Catalog item:

• Third Party \ BSP \ EVM_OMAP3530:ARMV4I \ Drivers \ PM \ Policy Adapter \ System state policy

## Smart Reflex Policy

This subsystem uses information written into write once memory in the OMAP35xx/DM37xx chip during factory testing. This information describes fine tuning that can be done to the OPPs (Operating Points). This driver requires the DVFS driver. This driver is enabled by select the following Catalog item:

• Third Party \ BSP \ EVM_OMAP3530:ARMV4I \ Drivers \ PM \ Policy Adapter \ SMART REFLEX

# Device Driver Specific Power Management Software

Some device drivers employ power management techniques that are not specific to either Windows CE6 or to the TI ARM_A8 processor family CPU design.

Display Driver Low Power Refresh: When driving only an LCD (Liquid Crystal Display) panel, the display driver may change the clocks used by the display controller to reduce power consumption. This may change the LCD refresh rate, but this will have no visual effect on modern active matrix LCD panels.

Device Driver Power Internal Management: Many device drivers directly manage the power consumption of resources used by the driver. This may be done independent of the system power state or the driver power state. Examples would be controlling clocks and power for the MMC/SD/SDIO socket or placing an external chip into low power mode when the driver is idle.

The following tabel shows the supported power states in each drivers.

 Device Prefix Power management capability (IOCTL_POWER_CAPABILITIES) IOCTL_POWER_SET USB OTG driver OTG D0, D4 Two levels: D0-D2, D3-D4 USB EHCI driver EHC D0, D4 D0, D4 Camera driver CAM D0, D4 Two levels: D0-D2, D3-D4 SDHC driver SHC D0, D4 D0, D4 backlight driver BKL D0, D1,D2,D3,D4 D0-D4, no real action Keypad driver KPD D0, D1,D2,D3,D4 D0-D4, no real action PowerVR PKM D0, D2, D4 D0-D2, D3-D4 wave driver(AM35x) WAV D0, D4 D0, D4 wave driver(OMAP35x) WAV D0, D4 D0, D4 RTC driver RTC D0, D4 D0, D4 TWL TWL D0, D2,D3,D4 D0, D1/D2,D3,D4 SPI driver SPI D0, D4 D0, D4 UART driver COM D0, D3, D4 D0->D3/D4, D3/D4->D0

# Suspend/Resume

## AM35x BSP Suspend/Resume

The EVM can be caused to suspend using:

• Desktop Start button menu, "Suspend" command.
• SetSystemPowerState(NULL, POWER_STATE_SUSPEND, 0) function call.
• GWES suspend timer timeout (disabled by default, but can be enabled by registry entries).

The EVM can be caused to resume using:

• RTC (Real Time Clock) Alarm (EVM2 only).
• Touch screen

## OMAP35x BSP Suspend/Resume

The EVM can be caused to suspend using:

• Desktop Start button menu, "Suspend" command.
• SetSystemPowerState(NULL, POWER_STATE_SUSPEND, 0) function call.
• Press the OMAP_PWR button.
• GWES suspend timer timeout (disabled by default, but can be enabled by registry entries).

The EVM can be caused to resume using:

• RTC (Real Time Clock) Alarm (EVM2 only).
• OMAP_PWR button.

# Measuring Power Consumption for TMDSEVM3530 and TMDXEVM3503 platform

The TMDSEVM3530 and TMDXEVM3503 platforms have some provisions for measuring power consumption of individual power supplies by measuring voltages using 2 pin headers on the main board. Note that a voltmeter with a millivolt (mV) range may be needed for accurate measurements. See the main board schematics for more information about these power measurement points.

Control of the OPM: The operating mode can be controlled using the Platform Builder target control shell "opm" command. This requires an image that has DVFS enabled.

If CPULOAD policy is enabled, the OPM (and VDD1 and VDD2 voltages) may vary according to system activity. Use of the Target Shell OPM command with the "-f" option may help to keep the voltages at fixed levels. If that does not work, then a special build with CPULOAD policy disabled may be needed.

The following table summarizes the information needed to do power measurament on TMDSEVM3530 and TMDXEVM3503 platforms.

When measuring voltage, measure voltage between ground and a pin on the Jumper. Note that one pin will be a slightly higher voltage than the other, use the higher voltage.

When measuring current, measure the voltage across the Jumper then dividing that voltage by "resistor value" in the following table to compute current.

The power measurement for DCIN cannot be performed without additional equipment to connect power to the DCIN jack of the EVM. If this is attempted, be sure that the voltage and polarity used match that of the supplied AC adapter. Use a bench power supply set to 5V to supply DCIN and measure the current supplied by bench supply.

 Jumper Resistor valuenote1 Typical Suspend Measurement for OMAP3530 Typical Suspend Measurement for DM3730 VDD1 J6 0.05 0 mA @ 0.001V (J6 0.05 Ohms) 0 mA @ 0.001V (J6 0.05 Ohms) VDD2 J5 0.1 0 mA @ 0.001V (J5 0.1 Ohms) 0 mA @ 0.009V (J5 0.1 Ohms) VIO J9 0.1 120 mA @ 1.8V (J9 0.1 Ohms) 120 mA @ 1.8V (J9 0.1 Ohms) VIO (CPU) J28 0.1 20 mA @ 1.8V (J28 0.1 Ohms) 70 mA @ 1.8V (J28 0.1 Ohms) VPLL1 J20 0.1 0 mA @ 1.8V (J20 0.1 Ohms) 0 mA @ 1.8V (J20 0.1 Ohms) VBAT_OSK J3 0.02 50 mA (J3 0.02 Ohms) 40mA (J3 0.02 Ohms) USB_3V3 J12 0.02 15 mA (J12 0.02 Ohms) 18 mA (J12 0.02 Ohms) DCIN NA NA 294 mA @ 5V 306 mA @ 5V

Note 1: This is the value of resistor that is in parallel with the Jumper for probing.

Typical Suspend State Power Measurements:

Typical suspend current measurements (in above table) are for the TMDSEVM3530 and the EVM_OMAP3530 BSP 1.00.14 release, DVFS disabled, SmartReflex disabled, OPM5(OMAP3530) or OPM3(DM3730), no device inserted in the USB EHCI port, SD card inserted and nothing connected to the serial ports.

# Known Power Management Issues

TMDSEVM3530 and TMDXEVM3503 Design: Some elements of the hardware designs limit the ability of the power management system to control power consumption, particularly in suspend. Examples include the Ethernet chip (no suspend mode), the video capture chip (power down pin not controlled), serial port level shifters (always on), power supplies/LEDs that are always on, and use of an EHCI USB port transceiver chip that has incompatibilities with the EHCI ULPI interface that prevent the USB bus from being placed into suspend mode . See the TMDSEVM3530 and TMDXEVM3503 schematics for more information.

Interrupt Latency: When the CPU enters the wait for interrupt state during idle periods (OEMIdle), the amount of time required for the CPU to return to normal operation and service an interrupt will depend on the configuration of the Interrupt Latency Constraint Management subsystem. If the interrupt latency times are longer than required, the configuration will have to be modified.

OPM6 Support: The BSP is configured for a maximum OPM of OPM5. Changes to the registry will be needed to enable full support for OPM6. Note that it is not known if the SmartReflex system will operate correctly with OPM6.

DSP Subsystem: The DSP subsystem does not interact with the power management subsystem running on the MPU. If the MPU is load is light, the OPM may be lowered even when the DSP load is high. This may be an issue because the MPU and DSP subsystems are controlled together when the OPM changes.

SmartReflex: The Smart Reflex feature will not work on DM37xx if the calibration data in EFUSE is not available.

See the BSP Release Notes for other known issues.